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Date:   Tue, 13 Aug 2019 11:48:32 +0200
From:   Thierry Reding <thierry.reding@gmail.com>
To:     Krishna Yarlagadda <kyarlagadda@nvidia.com>
Cc:     gregkh@linuxfoundation.org, robh+dt@kernel.org,
        mark.rutland@arm.com, jonathanh@nvidia.com, ldewangan@nvidia.com,
        jslaby@suse.com, linux-serial@vger.kernel.org,
        devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
        linux-kernel@vger.kernel.org,
        Shardar Shariff Md <smohammed@nvidia.com>
Subject: Re: [PATCH 05/14] serial: tegra: flush the RX fifo on frame error
Message-ID: <20190813094832.GJ1137@ulmo>
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On Mon, Aug 12, 2019 at 04:58:14PM +0530, Krishna Yarlagadda wrote:
> From: Shardar Shariff Md <smohammed@nvidia.com>
>=20
> FIFO reset/flush code implemented now does not follow programming
> guidelines. RTS line has to be turned off while flushing fifos to
> avoid new transfers. Also check LSR bits UART_LSR_TEMT and UART_LSR_DR
> to confirm fifos are flushed.

You use inconsistent spelling for FIFO here.

> Signed-off-by: Shardar Shariff Md <smohammed@nvidia.com>
> Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
> ---
>  drivers/tty/serial/serial-tegra.c | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
>=20
> diff --git a/drivers/tty/serial/serial-tegra.c b/drivers/tty/serial/seria=
l-tegra.c
> index ae7225c..f6a3f4e 100644
> --- a/drivers/tty/serial/serial-tegra.c
> +++ b/drivers/tty/serial/serial-tegra.c
> @@ -266,6 +266,10 @@ static void tegra_uart_wait_sym_time(struct tegra_ua=
rt_port *tup,
>  static void tegra_uart_fifo_reset(struct tegra_uart_port *tup, u8 fcr_bi=
ts)
>  {
>  	unsigned long fcr =3D tup->fcr_shadow;
> +	unsigned int lsr, tmout =3D 10000;
> +
> +	if (tup->rts_active)
> +		set_rts(tup, false);
> =20
>  	if (tup->cdata->allow_txfifo_reset_fifo_mode) {
>  		fcr |=3D fcr_bits & (UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
> @@ -289,6 +293,17 @@ static void tegra_uart_fifo_reset(struct tegra_uart_=
port *tup, u8 fcr_bits)
>  	 * to propagate, otherwise data could be lost.
>  	 */
>  	tegra_uart_wait_cycle_time(tup, 32);
> +
> +	do {
> +		lsr =3D tegra_uart_read(tup, UART_LSR);
> +		if (lsr | UART_LSR_TEMT)
> +			if (!(lsr & UART_LSR_DR))

Can't both of these go on the same line?

Thierry

> +				break;
> +		udelay(1);
> +	} while (--tmout);
> +
> +	if (tup->rts_active)
> +		set_rts(tup, true);
>  }
> =20
>  static int tegra_set_baudrate(struct tegra_uart_port *tup, unsigned int =
baud)
> --=20
> 2.7.4
>=20

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