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[209.132.180.67]) by mx.google.com with ESMTP id d4si819316pjj.28.2019.08.13.04.37.31; Tue, 13 Aug 2019 04:37:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=oYz8Uo6X; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727420AbfHMLgp (ORCPT + 99 others); Tue, 13 Aug 2019 07:36:45 -0400 Received: from hqemgate16.nvidia.com ([216.228.121.65]:8778 "EHLO hqemgate16.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725981AbfHMLgo (ORCPT ); Tue, 13 Aug 2019 07:36:44 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate16.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Tue, 13 Aug 2019 04:36:46 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Tue, 13 Aug 2019 04:36:44 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 13 Aug 2019 04:36:44 -0700 Received: from HQMAIL105.nvidia.com (172.20.187.12) by HQMAIL104.nvidia.com (172.18.146.11) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Tue, 13 Aug 2019 11:36:43 +0000 Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL105.nvidia.com (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Tue, 13 Aug 2019 11:36:43 +0000 Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Tue, 13 Aug 2019 04:36:43 -0700 From: Vidya Sagar To: , , , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH V16 01/13] PCI: Add #defines for some of PCIe spec r4.0 features Date: Tue, 13 Aug 2019 17:06:15 +0530 Message-ID: <20190813113627.27251-2-vidyas@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190813113627.27251-1-vidyas@nvidia.com> References: <20190813113627.27251-1-vidyas@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 Content-Type: text/plain DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1565696206; bh=Iv6ILrKrXPaU1PeyNvb+gzzCGAx9U6gAICpe2f5f5Hg=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=oYz8Uo6XAIu1X9fPetZi0gUK+N0zlDkg7Tr3lMObGVAxjNNQSY0g3o9m+VB3t26cW AwpepqBagsj9uRplyIdZgV4T1OvvdF6ysbBJ7wd/gzrRW9KCIov0kvT20J58+a2iEt JVZKPp2mnAKtWOOkfPFxHo8V/s45b29UlrRnOdCPNwZVSnyl5j3ivf+rR9SWkc0VLl sS2ghKsh1Ju3JNaKv6GaT4eLdE+wzMLIhKbyYJOaN+jHhGTYjifj+PiFprEk8o6rZt xUcOfMoy1g3Yde5eJHwyhUWGMjRuiHcUSiNK4ba6IY44HwRph/qJZBOjtzAiQTOJZ2 eQjnJi4b8DGGA== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add #defines only for the Data Link Feature and Physical Layer 16.0 GT/s features as defined in PCIe spec r4.0, sec 7.7.4 for Data Link Feature and sec 7.7.5 for Physical Layer 16.0 GT/s. Signed-off-by: Vidya Sagar Reviewed-by: Thierry Reding Acked-by: Bjorn Helgaas --- V16: * None V15: * None V14: * Added 'Acked-by: Bjorn Helgaas ' V13: * Updated commit message to include references from spec * Removed unused defines and moved some from pcie-tegra194.c file * Addressed review comments from Bjorn V12: * None V11: * None V10: * None V9: * None V8: * None V7: * None V6: * None V5: * None V4: * None V3: * Updated commit message and description to explicitly mention that defines are added only for some of the features and not all. V2: * None include/uapi/linux/pci_regs.h | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index f28e562d7ca8..d28d0319d932 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -713,7 +713,9 @@ #define PCI_EXT_CAP_ID_DPC 0x1D /* Downstream Port Containment */ #define PCI_EXT_CAP_ID_L1SS 0x1E /* L1 PM Substates */ #define PCI_EXT_CAP_ID_PTM 0x1F /* Precision Time Measurement */ -#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM +#define PCI_EXT_CAP_ID_DLF 0x25 /* Data Link Feature */ +#define PCI_EXT_CAP_ID_PL_16GT 0x26 /* Physical Layer 16.0 GT/s */ +#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_16GT #define PCI_EXT_CAP_DSN_SIZEOF 12 #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 @@ -1053,4 +1055,14 @@ #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE 0xe0000000 /* LTR_L1.2_THRESHOLD_Scale */ #define PCI_L1SS_CTL2 0x0c /* Control 2 Register */ +/* Data Link Feature */ +#define PCI_DLF_CAP 0x04 /* Capabilities Register */ +#define PCI_DLF_EXCHANGE_ENABLE 0x80000000 /* Data Link Feature Exchange Enable */ + +/* Physical Layer 16.0 GT/s */ +#define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */ +#define PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK 0x0000000F +#define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK 0x000000F0 +#define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT 4 + #endif /* LINUX_PCI_REGS_H */ -- 2.17.1