Received: by 2002:a25:8b12:0:0:0:0:0 with SMTP id i18csp1207664ybl; Tue, 13 Aug 2019 09:00:17 -0700 (PDT) X-Google-Smtp-Source: APXvYqx6wQV3HwZ3l2OV4MBbt3fCn8vpM3BnfNwem3vKP3XrpBL35QszsUr0LFbRSv3ycWdP2rKM X-Received: by 2002:a63:ff03:: with SMTP id k3mr35692198pgi.40.1565712017261; Tue, 13 Aug 2019 09:00:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1565712017; cv=none; d=google.com; s=arc-20160816; b=ENxV4YMSEV05i+f5HoDqiUctv3nyySk3X788LWWMDQrySPHgr1RGSS8BB+x3L+RCeD J1pkzats4F36fXQ2SkmBxJIiUQENybxUfCXJAPPzhSK1nxME5RdS1QaFcQiDPoABa5G8 35N/sOLlH8bVpRGObcgo7z8Q2tiLeS95hQ9AUfBk1kDTgohQ1s9NbBkzm+ej8Qtc+pkF RJ+/TSi1+ulipNDIbjrxGTiX9pnwzVwsRZgY1Cfa8j03oAp3JkvSgAJDXeiKU9WmD+N0 7+nfNH9k2+Dkx2e1etvuYOIJxFM6KckDscMp3grnEdAdRYn8u1ZWnm5t/Vf3aZUtw1h+ 9fZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=pgvdxjtpuz55YPGQB23L2WMX3O76fZRFK/d5NtZERoU=; b=qyGZ4tS6PP24Y7CfYRfS1qpPCp54S4p1r6f1x3dN8Qch48Acry86xenNjE2qqgKg3O I32+zCT5rPnU/2c43DX6a2uYJXwDNd/n/Ka3DGCdgZzf9be1vQccUBwhnmLg7vWLBAmk YMbQPD6jRg6EvEyQQGH3weUFhLU45s+9bVdH5/+NomVbZ6c9sLHWEKHH2tb+pBauQzug MRl/4bMVOHLmW1i94EDASc+/wPad3uYYjlTZe371A8hXCccBIdPppfFBDXbZviuCrudD 9xfWeF7ILDcGHysaGztw3/JM2LizWysZWTULZjgTIZNzgDqurqP+MPuqlJbjqcQNw/B+ EAOA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sifive.com header.s=google header.b=Eji9QCzX; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b18si58405387plz.389.2019.08.13.09.00.01; Tue, 13 Aug 2019 09:00:17 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@sifive.com header.s=google header.b=Eji9QCzX; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728170AbfHMMkS (ORCPT + 99 others); Tue, 13 Aug 2019 08:40:18 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:43387 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726974AbfHMMkR (ORCPT ); Tue, 13 Aug 2019 08:40:17 -0400 Received: by mail-pl1-f195.google.com with SMTP id 4so42238393pld.10 for ; Tue, 13 Aug 2019 05:40:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pgvdxjtpuz55YPGQB23L2WMX3O76fZRFK/d5NtZERoU=; b=Eji9QCzX6NDgNFeFnxj9rUaLJ6FyD9qbUp2fmHutJvjmJL8oz/oWGOEImUBp2qtzw2 ghphYL3aC6mXnLbOGCvXFQjrVBDpirAncbRbGmdUEa7XYLNB0D+JhD51PifiQw0pgHLw q1SDWN7dG9Glq6n0BucEoRp8nl9RhPMvVmD/hR9H22W/jI1JPRuB5KVf5Jet9+mUpmOT /GhnmfRF/XGkkEgiLzboxS9VhOmSkpz7xq5ZezpOIKH+oS6LIxMPzLR7H8po8iEM4nWL KuuymjgKjvPoiInOFUkLUoUWoDAkYK6WXeZiPva9HxTsOLsM0oeJH4zBeiBQoNloEkqW DKnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pgvdxjtpuz55YPGQB23L2WMX3O76fZRFK/d5NtZERoU=; b=ODPh7RviqNRuN2L8lsrcEpyg49/rt8hmmTeq/uhgELwqFG2WWklMsr+zOUZ3h8NEmw xll9+rXtFMas1MeDOq28jS/SwfZucKjEOUtG95FLTqsjtwRa1BgAgKDPnVvLg6+95hsJ rQ+s66bkzuuruXfTSFHnaU4VAraYoXqNdGwY8borAwlJGhAPucgrmrWsJ1Bi3ICcVpWR tkh1y11qRIIelldXQ/F3qKbxXlQbj2vqa94++cf+Wf7sAKMAYREg4LxJthV4csEwvmy2 QMxNgf99EFGWaE4ghCB65QRhD+OzH/yXrYn5tQovRe+vtTuIXk/YZU6ORKaFMvddrSQq gSwQ== X-Gm-Message-State: APjAAAVzmhMb5iNCn51+7ClhZS2bK+3SQZSuLVw6s9UyL8fkjy6pBcqu e7fW0uAtFdVBwyu8K2Tu3jhd9w== X-Received: by 2002:a17:902:20cc:: with SMTP id v12mr24385277plg.188.1565700017042; Tue, 13 Aug 2019 05:40:17 -0700 (PDT) Received: from buildserver-90.open-silicon.com ([114.143.65.226]) by smtp.googlemail.com with ESMTPSA id v145sm14758467pfc.31.2019.08.13.05.40.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 13 Aug 2019 05:40:16 -0700 (PDT) From: Sagar Shrikant Kadam To: marek.vasut@gmail.com, tudor.ambarus@microchip.com, dwmw2@infradead.org, computersforpeace@gmail.com, miquel.raynal@bootlin.com, richard@nod.at, vigneshr@ti.com Cc: paul.walmsley@sifive.com, palmer@sifive.com, aou@eecs.berkeley.edu, linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Sagar Shrikant Kadam Subject: [PATCH v8 1/4] mtd: spi-nor: add support for is25wp256 Date: Tue, 13 Aug 2019 18:08:12 +0530 Message-Id: <1565699895-4770-2-git-send-email-sagar.kadam@sifive.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1565699895-4770-1-git-send-email-sagar.kadam@sifive.com> References: <1565699895-4770-1-git-send-email-sagar.kadam@sifive.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Update spi_nor_id table for is25wp256 (32MB) device from ISSI, present on HiFive Unleashed dev board (Rev: A00). Set method to enable quad mode for ISSI device in flash parameters table. Based on code originally written by Wesley Terpstra and/or Palmer Dabbelt https://github.com/riscv/riscv-linux/commit/c94e267766d62bc9a669611c3d0c8ed5ea26569b Signed-off-by: Sagar Shrikant Kadam Reviewed-by: Vignesh Raghavendra --- drivers/mtd/spi-nor/spi-nor.c | 9 ++++++++- include/linux/mtd/spi-nor.h | 1 + 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c index 03cc788..6635127 100644 --- a/drivers/mtd/spi-nor/spi-nor.c +++ b/drivers/mtd/spi-nor/spi-nor.c @@ -1946,7 +1946,10 @@ static int spi_nor_spansion_clear_sr_bp(struct spi_nor *nor) SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { "is25wp128", INFO(0x9d7018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - + { "is25wp256", INFO(0x9d7019, 0, 64 * 1024, 1024, + SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | + SPI_NOR_4B_OPCODES) + }, /* Macronix */ { "mx25l512e", INFO(0xc22010, 0, 64 * 1024, 1, SECT_4K) }, { "mx25l2005a", INFO(0xc22012, 0, 64 * 1024, 4, SECT_4K) }, @@ -3776,6 +3779,10 @@ static int spi_nor_init_params(struct spi_nor *nor, case SNOR_MFR_ST: case SNOR_MFR_MICRON: break; + case SNOR_MFR_ISSI: + params->quad_enable = macronix_quad_enable; + break; + default: /* Kept only for backward compatibility purpose. */ diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 9f57cdf..5d6583e 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -21,6 +21,7 @@ #define SNOR_MFR_INTEL CFI_MFR_INTEL #define SNOR_MFR_ST CFI_MFR_ST /* ST Micro */ #define SNOR_MFR_MICRON CFI_MFR_MICRON /* Micron */ +#define SNOR_MFR_ISSI 0x9d /* ISSI */ #define SNOR_MFR_MACRONIX CFI_MFR_MACRONIX #define SNOR_MFR_SPANSION CFI_MFR_AMD #define SNOR_MFR_SST CFI_MFR_SST -- 1.9.1