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[209.132.180.67]) by mx.google.com with ESMTP id l40si25336837plb.205.2019.08.14.00.41.38; Wed, 14 Aug 2019 00:41:59 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727516AbfHNHjp (ORCPT + 99 others); Wed, 14 Aug 2019 03:39:45 -0400 Received: from metis.ext.pengutronix.de ([85.220.165.71]:54539 "EHLO metis.ext.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725265AbfHNHjp (ORCPT ); Wed, 14 Aug 2019 03:39:45 -0400 Received: from pty.hi.pengutronix.de ([2001:67c:670:100:1d::c5]) by metis.ext.pengutronix.de with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1hxnsi-00054p-8u; Wed, 14 Aug 2019 09:39:40 +0200 Received: from ukl by pty.hi.pengutronix.de with local (Exim 4.89) (envelope-from ) id 1hxnsh-0000zL-2k; Wed, 14 Aug 2019 09:39:39 +0200 Date: Wed, 14 Aug 2019 09:39:39 +0200 From: Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= To: Baolin Wang Cc: Thierry Reding , Rob Herring , Mark Rutland , Orson Zhai , Chunyan Zhang , Vincent Guittot , linux-pwm@vger.kernel.org, DTML , LKML Subject: Re: [PATCH v2 1/2] dt-bindings: pwm: sprd: Add Spreadtrum PWM documentation Message-ID: <20190814073939.ubgzysmkmmel5h4y@pengutronix.de> References: <20190813141256.jnbrfld42rtigek3@pengutronix.de> <20190814070121.o53tj2mtky4hcy3n@pengutronix.de> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: NeoMutt/20170113 (1.7.2) X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::c5 X-SA-Exim-Mail-From: ukl@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Aug 14, 2019 at 03:25:53PM +0800, Baolin Wang wrote: > Hi Uwe, > > On Wed, 14 Aug 2019 at 15:01, Uwe Kleine-K?nig > wrote: > > > > Hello Baolin, > > > > On Wed, Aug 14, 2019 at 09:51:34AM +0800, Baolin Wang wrote: > > > On Tue, 13 Aug 2019 at 22:13, Uwe Kleine-K?nig > > > wrote: > > > > On Tue, Aug 13, 2019 at 09:46:40PM +0800, Baolin Wang wrote: > > > > > +- assigned-clock-parents: The phandle of the parent clock of PWM clock. > > > > > > > > I'm not sure you need to point out assigned-clocks and > > > > assigned-clock-parents as this is general clk stuff. Also I wonder if > > > > these should be "required properties". > > > > > > I think I should describe any properties used by PWM node, like > > > 'clocks' and 'clock-names' properties, though they are common clock > > > properties. > > > > Then you might want to describe also "status", "assigned-clock-rates", > > "pinctrl-$n", "pinctrl-names", "power-domains", "power-domain-names" and > > probably another dozen I'm not aware of. > > We usually do not describe 'status', but if your device node used > "pinctrl-$n", "pinctrl-names" ... common properties, yes, you should > describe them to let users know what is the purpose of these > properties. That's also asked by DT maintainer Rob. Does this convince you that you should also describe "pinctrl-$n" and the others? If not, why not? We also usually don't describe assigned-clock-parents. For me these are all in the same catagory: Common properties supported for each devicetree node that represents a device. The only difference is that on your board you make use of some but not some others. > > > Yes, they are required. Thanks for your comments. > > > > required in which sense? Why can a Spreadtrum PWM not work when the > > clock parents are unspecified? > > On some Spreadtrum platforms, the default source clock of PWM may not > be enabled, so we should force users to select one available source > clock for PWM output clock. Sounds like a bug in the clk tree of your SoC that shouldn't affect how the PWM is described in the device tree. After all a parent of a clock is supposed to become enabled when the clock gets enabled. Best regards Uwe -- Pengutronix e.K. | Uwe Kleine-K?nig | Industrial Linux Solutions | http://www.pengutronix.de/ |