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Subject: RE: [EXT] Re: [v1 1/3] clk: ls1028a: Add clock driver for Display output interface
From:   Stephen Boyd <sboyd@kernel.org>
To:     "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
        "linux-devel@linux.nxdi.nxp.com" <linux-devel@linux.nxdi.nxp.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "liviu.dudau@arm.com" <liviu.dudau@arm.com>,
        Leo Li <leoyang.li@nxp.com>,
        Michael Turquette <mturquette@baylibre.com>,
        Wen He <wen.he_1@nxp.com>
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Date:   Wed, 14 Aug 2019 10:27:11 -0700
Message-Id: <20190814172712.7F8F6206C1@mail.kernel.org>
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Quoting Wen He (2019-08-14 02:38:21)
>=20
>=20
> > -----Original Message-----
> > From: Stephen Boyd <sboyd@kernel.org>
> > Sent: 2019=E5=B9=B48=E6=9C=8814=E6=97=A5 2:25
> > To: Michael Turquette <mturquette@baylibre.com>; Wen He
> > <wen.he_1@nxp.com>; Leo Li <leoyang.li@nxp.com>;
> > linux-clk@vger.kernel.org; linux-devel@linux.nxdi.nxp.com;
> > linux-kernel@vger.kernel.org; liviu.dudau@arm.com
> > Cc: Wen He <wen.he_1@nxp.com>
> > Subject: [EXT] Re: [v1 1/3] clk: ls1028a: Add clock driver for Display =
output
> > interface
> >=20
> >=20
> > Quoting Wen He (2019-08-12 03:01:03)
> > > diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index
> > > 801fa1cd0321..0e6c7027d637 100644
> > > --- a/drivers/clk/Kconfig
> > > +++ b/drivers/clk/Kconfig
> > > @@ -223,6 +223,15 @@ config CLK_QORIQ
> > >           This adds the clock driver support for Freescale QorIQ plat=
forms
> > >           using common clock framework.
> > >
> > > +config CLK_PLLDIG
> > > +        bool "Clock driver for LS1028A Display output"
> > > +        depends on ARCH_LAYERSCAPE && OF
> >=20
> > Does it actually depend on either of these to build? Probabl not, so ma=
ybe just
> > default ARCH_LAYERSCAPE && OF? Also, can your Kconfig variable be named
> > something more specific like CLK_LS1028A_PLLDIG?
>=20
> Actually it also depends Display modules, but we allow building display d=
rivers as modules,=20
> so is here whether need add Display modules depend and also allow clock d=
river building
> to a module?=20
> Would it be better to reduce the number of the modules insert, I think th=
e clock driver
> should be long available for the system.

I'm asking if it actually requires ARCH_LAYERSCAPE or OF to successfully
compile the file. Is that true? I don't see any asm/ includes or
anything that's going to fail if either of these configs aren't enabled.
So it seems safe to change this to=20

	depends on ARCH_LAYERSCAPE || COMPILE_TEST
	default ARCH_LAYERSCAPE

so that it's compiled by default on this architecture and is available
to be compile tested by various test builders.

>=20
> looks like great if named Kconfig variable to 'CLK_LS1028A_PLLDIG'.
>=20
> >=20