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From:   "Suthikulpanit, Suravee" <Suravee.Suthikulpanit@amd.com>
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        "kvm@vger.kernel.org" <kvm@vger.kernel.org>
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        "Grimm, Jon" <Jon.Grimm@amd.com>,
        "Suthikulpanit, Suravee" <Suravee.Suthikulpanit@amd.com>
Subject: [PATCH v2 12/15] kvm: i8254: Check LAPIC EOI pending when injecting
 irq on SVM AVIC
Thread-Topic: [PATCH v2 12/15] kvm: i8254: Check LAPIC EOI pending when
 injecting irq on SVM AVIC
Thread-Index: AQHVU4YGnOwcrgTvnU6R6KE2IzCt1w==
Date:   Thu, 15 Aug 2019 16:25:17 +0000
Message-ID: <1565886293-115836-13-git-send-email-suravee.suthikulpanit@amd.com>
References: <1565886293-115836-1-git-send-email-suravee.suthikulpanit@amd.com>
In-Reply-To: <1565886293-115836-1-git-send-email-suravee.suthikulpanit@amd.com>
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ACK notifiers don't work with AMD SVM w/ AVIC when the PIT interrupt
is delivered as edge-triggered fixed interrupt since AMD processors
cannot exit on EOI for these interrupts.

Add code to check LAPIC pending EOI before injecting any pending PIT
interrupt on AMD SVM when AVIC is activated.

Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
---
 arch/x86/kvm/i8254.c | 31 +++++++++++++++++++++++++------
 1 file changed, 25 insertions(+), 6 deletions(-)

diff --git a/arch/x86/kvm/i8254.c b/arch/x86/kvm/i8254.c
index 4a6dc54..31c4a9b 100644
--- a/arch/x86/kvm/i8254.c
+++ b/arch/x86/kvm/i8254.c
@@ -34,10 +34,12 @@
=20
 #include <linux/kvm_host.h>
 #include <linux/slab.h>
+#include <asm/virtext.h>
=20
 #include "ioapic.h"
 #include "irq.h"
 #include "i8254.h"
+#include "lapic.h"
 #include "x86.h"
=20
 #ifndef CONFIG_X86_64
@@ -236,6 +238,12 @@ static void destroy_pit_timer(struct kvm_pit *pit)
 	kthread_flush_work(&pit->expired);
 }
=20
+static inline void kvm_pit_reset_reinject(struct kvm_pit *pit)
+{
+	atomic_set(&pit->pit_state.pending, 0);
+	atomic_set(&pit->pit_state.irq_ack, 1);
+}
+
 static void pit_do_work(struct kthread_work *work)
 {
 	struct kvm_pit *pit =3D container_of(work, struct kvm_pit, expired);
@@ -244,6 +252,23 @@ static void pit_do_work(struct kthread_work *work)
 	int i;
 	struct kvm_kpit_state *ps =3D &pit->pit_state;
=20
+	/*
+	 * Since, AMD SVM AVIC accelerates write access to APIC EOI
+	 * register for edge-trigger interrupts. PIT will not be able
+	 * to receive the IRQ ACK notifier and will always be zero.
+	 * Therefore, we check if any LAPIC EOI pending for vector 0
+	 * and reset irq_ack if no pending.
+	 */
+	if (cpu_has_svm(NULL) && kvm->arch.apicv_state =3D=3D APICV_ACTIVATED) {
+		int eoi =3D 0;
+
+		kvm_for_each_vcpu(i, vcpu, kvm)
+			if (kvm_apic_pending_eoi(vcpu, 0))
+				eoi++;
+		if (!eoi)
+			kvm_pit_reset_reinject(pit);
+	}
+
 	if (atomic_read(&ps->reinject) && !atomic_xchg(&ps->irq_ack, 0))
 		return;
=20
@@ -281,12 +306,6 @@ static enum hrtimer_restart pit_timer_fn(struct hrtime=
r *data)
 		return HRTIMER_NORESTART;
 }
=20
-static inline void kvm_pit_reset_reinject(struct kvm_pit *pit)
-{
-	atomic_set(&pit->pit_state.pending, 0);
-	atomic_set(&pit->pit_state.irq_ack, 1);
-}
-
 void kvm_pit_set_reinject(struct kvm_pit *pit, bool reinject)
 {
 	struct kvm_kpit_state *ps =3D &pit->pit_state;
--=20
1.8.3.1