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From:   "Suthikulpanit, Suravee" <Suravee.Suthikulpanit@amd.com>
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        "kvm@vger.kernel.org" <kvm@vger.kernel.org>
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        "Grimm, Jon" <Jon.Grimm@amd.com>,
        "Suthikulpanit, Suravee" <Suravee.Suthikulpanit@amd.com>
Subject: [PATCH v2 14/15] kvm: ioapic: Delay update IOAPIC EOI for RTC
Thread-Topic: [PATCH v2 14/15] kvm: ioapic: Delay update IOAPIC EOI for RTC
Thread-Index: AQHVU4YIh6tJvHdq80Sa2/XMOGUQVA==
Date:   Thu, 15 Aug 2019 16:25:20 +0000
Message-ID: <1565886293-115836-15-git-send-email-suravee.suthikulpanit@amd.com>
References: <1565886293-115836-1-git-send-email-suravee.suthikulpanit@amd.com>
In-Reply-To: <1565886293-115836-1-git-send-email-suravee.suthikulpanit@amd.com>
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In-kernel IOAPIC does not update RTC pending EOI info with AMD SVM /w AVIC
when interrupt is delivered as edge-triggered since AMD processors
cannot exit on EOI for these interrupts.

Add code to also check LAPIC pending EOI before injecting any new RTC
interrupts on AMD SVM when AVIC is activated.

Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
---
 arch/x86/kvm/ioapic.c | 36 ++++++++++++++++++++++++++++++++----
 1 file changed, 32 insertions(+), 4 deletions(-)

diff --git a/arch/x86/kvm/ioapic.c b/arch/x86/kvm/ioapic.c
index 1add1bc..45e7bb0 100644
--- a/arch/x86/kvm/ioapic.c
+++ b/arch/x86/kvm/ioapic.c
@@ -39,6 +39,7 @@
 #include <asm/processor.h>
 #include <asm/page.h>
 #include <asm/current.h>
+#include <asm/virtext.h>
 #include <trace/events/kvm.h>
=20
 #include "ioapic.h"
@@ -173,6 +174,7 @@ static bool rtc_irq_check_coalesced(struct kvm_ioapic *=
ioapic)
 	return false;
 }
=20
+#define APIC_DEST_NOSHORT		0x0
 static int ioapic_set_irq(struct kvm_ioapic *ioapic, unsigned int irq,
 		int irq_level, bool line_status)
 {
@@ -201,10 +203,36 @@ static int ioapic_set_irq(struct kvm_ioapic *ioapic, =
unsigned int irq,
 	 * interrupts lead to time drift in Windows guests.  So we track
 	 * EOI manually for the RTC interrupt.
 	 */
-	if (irq =3D=3D RTC_GSI && line_status &&
-		rtc_irq_check_coalesced(ioapic)) {
-		ret =3D 0;
-		goto out;
+	if (irq =3D=3D RTC_GSI && line_status) {
+		struct kvm *kvm =3D ioapic->kvm;
+		union kvm_ioapic_redirect_entry *entry =3D &ioapic->redirtbl[irq];
+
+		/*
+		 * Since, AMD SVM AVIC accelerates write access to APIC EOI
+		 * register for edge-trigger interrupts, IOAPIC will not be
+		 * able to receive the EOI. In this case, we do lazy update
+		 * of the pending EOI when trying to set IOAPIC irq for RTC.
+		 */
+		if (cpu_has_svm(NULL) &&
+		    (kvm->arch.apicv_state =3D=3D APICV_ACTIVATED) &&
+		    (entry->fields.trig_mode =3D=3D IOAPIC_EDGE_TRIG)) {
+			int i;
+			struct kvm_vcpu *vcpu;
+
+			kvm_for_each_vcpu(i, vcpu, kvm)
+				if (kvm_apic_match_dest(vcpu, NULL,
+							KVM_APIC_DEST_NOSHORT,
+							entry->fields.dest_id,
+							entry->fields.dest_mode)) {
+					__rtc_irq_eoi_tracking_restore_one(vcpu);
+					break;
+				}
+		}
+
+		if (rtc_irq_check_coalesced(ioapic)) {
+			ret =3D 0;
+			goto out;
+		}
 	}
=20
 	old_irr =3D ioapic->irr;
--=20
1.8.3.1