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[209.132.180.67]) by mx.google.com with ESMTP id b20si3224190pgl.533.2019.08.16.00.23.33; Fri, 16 Aug 2019 00:24:00 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726826AbfHPHWN (ORCPT + 99 others); Fri, 16 Aug 2019 03:22:13 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:25143 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726634AbfHPHWN (ORCPT ); Fri, 16 Aug 2019 03:22:13 -0400 X-UUID: d49054488efc4eb6997fa908461bf604-20190816 X-UUID: d49054488efc4eb6997fa908461bf604-20190816 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0707 with TLS) with ESMTP id 1658573712; Fri, 16 Aug 2019 15:22:06 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 16 Aug 2019 15:22:07 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 16 Aug 2019 15:22:07 +0800 From: Sam Shih To: Rob Herring , Mark Rutland , Matthias Brugger , Thierry Reding CC: Ryder Lee , John Crispin , , , , , Sam Shih Subject: [PATCH v3 1/10] pwm: mediatek: add a property "num-pwms" Date: Fri, 16 Aug 2019 15:21:19 +0800 Message-ID: <1565940088-845-2-git-send-email-sam.shih@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1565940088-845-1-git-send-email-sam.shih@mediatek.com> References: <1565940088-845-1-git-send-email-sam.shih@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-SNTS-SMTP: 0C902ACE32ECD8BBAAFC990D921AF25369D49794EA9493C6726966A50E95A3502000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ryder Lee This adds a property "num-pwms" to avoid having an endless list of compatibles with no differences for the same driver. Signed-off-by: Ryder Lee Signed-off-by: Sam Shih --- drivers/pwm/pwm-mediatek.c | 35 ++++++++++++++++++++++------------- 1 file changed, 22 insertions(+), 13 deletions(-) diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c index eb6674ce995f..f9d67fb66adb 100644 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c @@ -55,7 +55,7 @@ static const char * const mtk_pwm_clk_name[MTK_CLK_MAX] = { }; struct mtk_pwm_platform_data { - unsigned int num_pwms; + unsigned int fallback_npwms; bool pwm45_fixup; bool has_clks; }; @@ -226,27 +226,36 @@ static const struct pwm_ops mtk_pwm_ops = { static int mtk_pwm_probe(struct platform_device *pdev) { - const struct mtk_pwm_platform_data *data; + struct device_node *np = pdev->dev.of_node; struct mtk_pwm_chip *pc; struct resource *res; - unsigned int i; + unsigned int i, npwms; int ret; pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); if (!pc) return -ENOMEM; - data = of_device_get_match_data(&pdev->dev); - if (data == NULL) - return -EINVAL; - pc->soc = data; + pc->soc = of_device_get_match_data(&pdev->dev); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); pc->regs = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(pc->regs)) return PTR_ERR(pc->regs); - for (i = 0; i < data->num_pwms + 2 && pc->soc->has_clks; i++) { + ret = of_property_read_u32(np, "num-pwms", &npwms); + if (ret < 0) { + /* It's deprecated, we should specify num_pwms via DT now. */ + if (pc->soc->fallback_npwms) { + npwms = pc->soc->fallback_npwms; + dev_warn(&pdev->dev, "DT is outdated, please update it\n"); + } else { + dev_err(&pdev->dev, "failed to get number of PWMs\n"); + return ret; + } + } + + for (i = 0; i < npwms + 2 && pc->soc->has_clks; i++) { pc->clks[i] = devm_clk_get(&pdev->dev, mtk_pwm_clk_name[i]); if (IS_ERR(pc->clks[i])) { dev_err(&pdev->dev, "clock: %s fail: %ld\n", @@ -260,7 +269,7 @@ static int mtk_pwm_probe(struct platform_device *pdev) pc->chip.dev = &pdev->dev; pc->chip.ops = &mtk_pwm_ops; pc->chip.base = -1; - pc->chip.npwm = data->num_pwms; + pc->chip.npwm = npwms; ret = pwmchip_add(&pc->chip); if (ret < 0) { @@ -279,25 +288,25 @@ static int mtk_pwm_remove(struct platform_device *pdev) } static const struct mtk_pwm_platform_data mt2712_pwm_data = { - .num_pwms = 8, + .fallback_npwms = 8, .pwm45_fixup = false, .has_clks = true, }; static const struct mtk_pwm_platform_data mt7622_pwm_data = { - .num_pwms = 6, + .fallback_npwms = 6, .pwm45_fixup = false, .has_clks = true, }; static const struct mtk_pwm_platform_data mt7623_pwm_data = { - .num_pwms = 5, + .fallback_npwms = 5, .pwm45_fixup = true, .has_clks = true, }; static const struct mtk_pwm_platform_data mt7628_pwm_data = { - .num_pwms = 4, + .fallback_npwms = 4, .pwm45_fixup = true, .has_clks = false, }; -- 2.17.1