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([2a01:e34:ed2f:f020:d4e8:1742:2f00:abef]) by smtp.googlemail.com with ESMTPSA id a19sm18399286wra.2.2019.08.16.08.09.07 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 16 Aug 2019 08:09:08 -0700 (PDT) Subject: Re: [PATCH v2 1/5] RISC-V: Remove per cpu clocksource To: Atish Patra , linux-kernel@vger.kernel.org Cc: Albert Ou , Alexios Zavras , Allison Randal , Anup Patel , devicetree@vger.kernel.org, Enrico Weigelt , Greg Kroah-Hartman , Johan Hovold , linux-riscv@lists.infradead.org, Mark Rutland , Palmer Dabbelt , Paul Walmsley , Rob Herring , Thomas Gleixner References: <20190731012418.24565-1-atish.patra@wdc.com> <20190731012418.24565-2-atish.patra@wdc.com> From: Daniel Lezcano Openpgp: preference=signencrypt Autocrypt: addr=daniel.lezcano@linaro.org; prefer-encrypt=mutual; keydata= mQINBFv/yykBEADDdW8RZu7iZILSf3zxq5y8YdaeyZjI/MaqgnvG/c3WjFaunoTMspeusiFE sXvtg3ehTOoyD0oFjKkHaia1Zpa1m/gnNdT/WvTveLfGA1gH+yGes2Sr53Ht8hWYZFYMZc8V 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qePOXubgouxumi5RQs1+crBmCDa/AyJHKdG2mqCt9fx5EPbDpw6Zzx7hgURh4ikHoS7/tLjK iqWjuat8/HWc01yEd8rtkGuUcMqbCi1XhcAmkaOnX8FYscMRoyyMrWClRZEQRokqZIj79+PR adkDXtr4MeL8BaB7Ij2oyRVjXUwhFQNKi5Z5Rve0a3zvGkkqw8Mz20BOksjSWjAF6g9byukl CUVjC03PdMSufNLK06x5hPc/c4tFR4J9cLrV+XxdCX7r0zGos9SzTPGNuIk1LK++S3EJhLFj 4eoWtNhMWc1uiTf9ENza0ntqH9XBWEQ6IA1gubCniGG+Xg== Message-ID: <6ba37c45-2d9b-c01e-5f17-3ab919da4de8@linaro.org> Date: Fri, 16 Aug 2019 17:09:07 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20190731012418.24565-2-atish.patra@wdc.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 31/07/2019 03:24, Atish Patra wrote: > There is only one clocksource in RISC-V. The boot cpu initializes > that clocksource. No need to keep a percpu data structure. That is not what is stated in the initial patch [1]. Can you clarify that ? Thanks -- Daniel [1] https://lkml.org/lkml/2018/8/4/51 > Signed-off-by: Atish Patra > --- > drivers/clocksource/timer-riscv.c | 6 ++---- > 1 file changed, 2 insertions(+), 4 deletions(-) > > diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c > index 5e6038fbf115..09e031176bc6 100644 > --- a/drivers/clocksource/timer-riscv.c > +++ b/drivers/clocksource/timer-riscv.c > @@ -55,7 +55,7 @@ static u64 riscv_sched_clock(void) > return get_cycles64(); > } > > -static DEFINE_PER_CPU(struct clocksource, riscv_clocksource) = { > +static struct clocksource riscv_clocksource = { > .name = "riscv_clocksource", > .rating = 300, > .mask = CLOCKSOURCE_MASK(64), > @@ -92,7 +92,6 @@ void riscv_timer_interrupt(void) > static int __init riscv_timer_init_dt(struct device_node *n) > { > int cpuid, hartid, error; > - struct clocksource *cs; > > hartid = riscv_of_processor_hartid(n); > if (hartid < 0) { > @@ -112,8 +111,7 @@ static int __init riscv_timer_init_dt(struct device_node *n) > > pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n", > __func__, cpuid, hartid); > - cs = per_cpu_ptr(&riscv_clocksource, cpuid); > - error = clocksource_register_hz(cs, riscv_timebase); > + error = clocksource_register_hz(&riscv_clocksource, riscv_timebase); > if (error) { > pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", > error, cpuid); > -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog