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[209.132.180.67]) by mx.google.com with ESMTP id 69si4825847plc.411.2019.08.16.14.46.30; Fri, 16 Aug 2019 14:46:46 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@google.com header.s=20161025 header.b=bR6jRalC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=google.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727766AbfHPVpw (ORCPT + 99 others); Fri, 16 Aug 2019 17:45:52 -0400 Received: from mail-io1-f65.google.com ([209.85.166.65]:41883 "EHLO mail-io1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727756AbfHPVpv (ORCPT ); Fri, 16 Aug 2019 17:45:51 -0400 Received: by mail-io1-f65.google.com with SMTP id j5so9127688ioj.8 for ; Fri, 16 Aug 2019 14:45:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=OJfTLw9HSdNJm60I6uHAdDZzXWuRnU4z9y6bRN6cjWc=; b=bR6jRalCIevq0ABoPuEl+Eq5L3NPtBnWeWiPN6gDyoSRG9W3Oug49waSn0b2wcOuqE mLn5q9cZWGTUD2uCOQsX/3YyybikGIdtBpKTFbQSl6WODe6Qj5V8LQxMDhl2J8/8Mlqe PB+MIDgCC2Cb10JGUeb55QghgaT4OQeE3CiTjNfW+aHvh88Vb0u/01ioxETMCcUETfhM pUY0CDbvV1ZrmexMFsrb1Ua5cm7yg5FHv+xdNqj2Kk5nMw4AghSrmNQthLlw2jB9mdgT B7k+ODKNuu+0SAP5EIxWAl1wFjzVkoqlDnPYldXHEhU/yDFA9uAFuFKiZiaDpYwuxElg OBLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=OJfTLw9HSdNJm60I6uHAdDZzXWuRnU4z9y6bRN6cjWc=; b=Kkfbzf1NZeUsmCK9md7GTW5rnaescLXYxQoKJ2ORY17+qISIxDsyL4VnaF+CIAUrBj v47K9plu02oi8n4odbfuoTv66moefCam85vrOCywW83HHtRkmfxO6DJFY/e8QfV+LSnf YMzIwxYuZa9eYLc/ZAbymtiVYKEwHWUrSlrIYRBHoKZtApRUn04MDfkn3vQib3bfKOy9 chOjgHtK3onVhDLtuStCJdgVMPqWuAn9kCwtlTdxqubycqsHUkUlRr4dK4whkIrONSL7 b51lWLwGto/9Vkuck4AaOrZQ4Od1UU4cQxzzjN7gpz4cvQwzQmzTA9VxacEVohhixlN6 MHpA== X-Gm-Message-State: APjAAAVOMTfy8CgcABdHCJtPuPx2giNUrhh1vH9NkcRrtY73YLJRULcZ 0YdBJfFcSI+rBLjQGalHr1uiOw7e/BYWtcKJcr81YA== X-Received: by 2002:a02:a405:: with SMTP id c5mr13413575jal.54.1565991950591; Fri, 16 Aug 2019 14:45:50 -0700 (PDT) MIME-Version: 1.0 References: <1565854883-27019-1-git-send-email-pbonzini@redhat.com> <1565854883-27019-2-git-send-email-pbonzini@redhat.com> In-Reply-To: <1565854883-27019-2-git-send-email-pbonzini@redhat.com> From: Jim Mattson Date: Fri, 16 Aug 2019 14:45:39 -0700 Message-ID: Subject: Re: [PATCH 1/2] KVM: x86: fix reporting of AMD speculation bug CPUID leaf To: Paolo Bonzini Cc: LKML , kvm list Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, Aug 15, 2019 at 12:41 AM Paolo Bonzini wrote: > > The AMD_* bits have to be set from the vendor-independent > feature and bug flags, because KVM_GET_SUPPORTED_CPUID does not care > about the vendor and they should be set on Intel processors as well. > On top of this, SSBD, STIBP and AMD_SSB_NO bit were not set, and > VIRT_SSBD does not have to be added manually because it is a > cpufeature that comes directly from the host's CPUID bit. > > Signed-off-by: Paolo Bonzini On AMD systems, aren't AMD_SSBD, AMD_STIBP, and AMD_SSB_NO set by inheritance from the host: /* cpuid 0x80000008.ebx */ const u32 kvm_cpuid_8000_0008_ebx_x86_features = F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON); I am curious why the cross-vendor settings go only one way. For example, you set AMD_STIBP on Intel processors that have STIBP, but you do not set INTEL_STIBP on AMD processors that have STIBP? Similarly, you set AMD_SSB_NO for Intel processors that are immune to SSB, but you do not set IA32_ARCH_CAPABILITIES.SSB_NO for AMD processors that are immune to SSB? Perhaps there is another patch coming for reporting Intel bits on AMD?