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[209.132.180.67]) by mx.google.com with ESMTP id f186si9500608pgc.438.2019.08.19.04.07.56; Mon, 19 Aug 2019 04:08:12 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=kcw+WeOb; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727039AbfHSLG7 (ORCPT + 99 others); Mon, 19 Aug 2019 07:06:59 -0400 Received: from mail.kernel.org ([198.145.29.99]:52784 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726477AbfHSLG7 (ORCPT ); Mon, 19 Aug 2019 07:06:59 -0400 Received: from X250 (37.80-203-192.nextgentel.com [80.203.192.37]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 449C720844; Mon, 19 Aug 2019 11:06:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1566212818; bh=FTtPghP4JhraCtk0Ky8Cw09VOBcrHb9sW6Gmu2Y9IbA=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=kcw+WeObE43jKg5SXlqiybEn0zF6OT4mLmNoQJl6smmrg721oVFWfcWYAMMlKDUui H6tKRaaWRYSmIOxjPPTS5kQE0XJgqpr/iRMi7efCwK5TDqdy+ecK7/3qJA5U+t5nsq 5avA7J9KEAcbb9vOoOeHuh85ZbfxvAuOv8pyL9fo= Date: Mon, 19 Aug 2019 13:06:46 +0200 From: Shawn Guo To: Philippe Schenker Cc: Marcel Ziswiler , Max Krummenacher , "stefan@agner.ch" , "devicetree@vger.kernel.org" , Rob Herring , Mark Rutland , Michal =?utf-8?B?Vm9rw6HEjQ==?= , Fabio Estevam , Stefan Agner , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Pengutronix Kernel Team , NXP Linux Team , Sascha Hauer Subject: Re: [PATCH v4 02/21] ARM: dts: imx7-colibri: disable HS400 Message-ID: <20190819110645.GL5999@X250> References: <20190812142105.1995-1-philippe.schenker@toradex.com> <20190812142105.1995-3-philippe.schenker@toradex.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190812142105.1995-3-philippe.schenker@toradex.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Aug 12, 2019 at 02:21:17PM +0000, Philippe Schenker wrote: > From: Stefan Agner > > Force HS200 by masking bit 63 of the SDHCI capability register. > The i.MX ESDHC driver uses SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400. With > that the stack checks bit 63 to descide whether HS400 is available. > Using sdhci-caps-mask allows to mask bit 63. The stack then selects > HS200 as operating mode. > > This prevents rare communication errors with minimal effect on > performance: > sdhci-esdhc-imx 30b60000.usdhc: warning! HS400 strobe DLL > status REF not lock! > > Signed-off-by: Stefan Agner > Signed-off-by: Philippe Schenker Applied, thanks.