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[209.132.180.67]) by mx.google.com with ESMTP id l185si9615026pgd.379.2019.08.19.04.20.21; Mon, 19 Aug 2019 04:20:36 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b=DmQrUeLX; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727447AbfHSLTC (ORCPT + 99 others); Mon, 19 Aug 2019 07:19:02 -0400 Received: from mail.kernel.org ([198.145.29.99]:33500 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726694AbfHSLTC (ORCPT ); Mon, 19 Aug 2019 07:19:02 -0400 Received: from X250 (37.80-203-192.nextgentel.com [80.203.192.37]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id CC9F42085A; Mon, 19 Aug 2019 11:18:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1566213541; bh=wUOaCEaWH+zGwPwJEP4cQs1+4O414saVr5gYOrQZAfY=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=DmQrUeLXoNKvO5IHeTW93qHddpzI3CploHgntA27j1EmqglqU89plun/se6FkVdhZ By2Fc3Fi1Ikpw6Ms5sSgpdpgJIbzDXCY7mFQUj3ZTfIx0FFWMyEmt90V5pQT6LHQ2A oxx5y4i8eocRaYyhM1YcTL0HnBTqZDzfUtuvgdPU= Date: Mon, 19 Aug 2019 13:18:48 +0200 From: Shawn Guo To: Philippe Schenker Cc: Marcel Ziswiler , Max Krummenacher , "stefan@agner.ch" , "devicetree@vger.kernel.org" , Rob Herring , Mark Rutland , Michal =?utf-8?B?Vm9rw6HEjQ==?= , Fabio Estevam , Stefan Agner , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Pengutronix Kernel Team , NXP Linux Team , Sascha Hauer Subject: Re: [PATCH v4 07/21] ARM: dts: imx7-colibri: fix 1.8V/UHS support Message-ID: <20190819111847.GQ5999@X250> References: <20190812142105.1995-1-philippe.schenker@toradex.com> <20190812142105.1995-8-philippe.schenker@toradex.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190812142105.1995-8-philippe.schenker@toradex.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Aug 12, 2019 at 02:21:25PM +0000, Philippe Schenker wrote: > From: Stefan Agner > > Add pinmuxing and do not specify voltage restrictions for the usdhc > instance available on the modules edge connector. This allows to use > SD-cards with higher transfer modes if supported by the carrier board. > > Signed-off-by: Stefan Agner > Signed-off-by: Philippe Schenker > Acked-by: Marcel Ziswiler > > --- > > Changes in v4: > - Add Marcel Ziswiler's Ack > > Changes in v3: > - Add new commit message from Stefan's proposal on ML > > Changes in v2: None > > arch/arm/boot/dts/imx7-colibri.dtsi | 23 ++++++++++++++++++++++- > 1 file changed, 22 insertions(+), 1 deletion(-) > > diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi > index 5347ed38acb2..c563bb821b5e 100644 > --- a/arch/arm/boot/dts/imx7-colibri.dtsi > +++ b/arch/arm/boot/dts/imx7-colibri.dtsi > @@ -326,7 +326,6 @@ > &usdhc1 { > pinctrl-names = "default"; > pinctrl-0 = <&pinctrl_usdhc1 &pinctrl_cd_usdhc1>; > - no-1-8-v; > cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; > disable-wp; > vqmmc-supply = <®_LDO2>; > @@ -671,6 +670,28 @@ > >; > }; > > + pinctrl_usdhc1_100mhz: usdhc1grp_100mhz { > + fsl,pins = < > + MX7D_PAD_SD1_CMD__SD1_CMD 0x5a > + MX7D_PAD_SD1_CLK__SD1_CLK 0x1a > + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5a > + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5a > + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5a > + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5a > + >; > + }; > + > + pinctrl_usdhc1_200mhz: usdhc1grp_200mhz { No reference to them from usdhc1 node? Shawn > + fsl,pins = < > + MX7D_PAD_SD1_CMD__SD1_CMD 0x5b > + MX7D_PAD_SD1_CLK__SD1_CLK 0x1b > + MX7D_PAD_SD1_DATA0__SD1_DATA0 0x5b > + MX7D_PAD_SD1_DATA1__SD1_DATA1 0x5b > + MX7D_PAD_SD1_DATA2__SD1_DATA2 0x5b > + MX7D_PAD_SD1_DATA3__SD1_DATA3 0x5b > + >; > + }; > + > pinctrl_usdhc3: usdhc3grp { > fsl,pins = < > MX7D_PAD_SD3_CMD__SD3_CMD 0x59 > -- > 2.22.0 >