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([2001:b07:6468:f312:8033:56b6:f047:ba4f]) by smtp.gmail.com with ESMTPSA id o5sm12416090wrv.20.2019.08.19.08.18.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 19 Aug 2019 08:18:00 -0700 (PDT) Subject: Re: [PATCH 1/2] KVM: x86: fix reporting of AMD speculation bug CPUID leaf To: Jim Mattson Cc: LKML , kvm list References: <1565854883-27019-1-git-send-email-pbonzini@redhat.com> <1565854883-27019-2-git-send-email-pbonzini@redhat.com> From: Paolo Bonzini Message-ID: <0e29f624-10f5-7ab5-1823-280f32732b68@redhat.com> Date: Mon, 19 Aug 2019 17:18:04 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 16/08/19 23:45, Jim Mattson wrote: > On Thu, Aug 15, 2019 at 12:41 AM Paolo Bonzini wrote: >> >> The AMD_* bits have to be set from the vendor-independent >> feature and bug flags, because KVM_GET_SUPPORTED_CPUID does not care >> about the vendor and they should be set on Intel processors as well. >> On top of this, SSBD, STIBP and AMD_SSB_NO bit were not set, and >> VIRT_SSBD does not have to be added manually because it is a >> cpufeature that comes directly from the host's CPUID bit. >> >> Signed-off-by: Paolo Bonzini > > On AMD systems, aren't AMD_SSBD, AMD_STIBP, and AMD_SSB_NO set by > inheritance from the host: > > /* cpuid 0x80000008.ebx */ > const u32 kvm_cpuid_8000_0008_ebx_x86_features = > F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | > F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON); > > I am curious why the cross-vendor settings go only one way. For > example, you set AMD_STIBP on Intel processors that have STIBP, but > you do not set INTEL_STIBP on AMD processors that have STIBP? > Similarly, you set AMD_SSB_NO for Intel processors that are immune to > SSB, but you do not set IA32_ARCH_CAPABILITIES.SSB_NO for AMD > processors that are immune to SSB? > > Perhaps there is another patch coming for reporting Intel bits on AMD? I wasn't going to work on it but yes, they should be. This patch just fixed what was half-implemented. Paolo