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From:   Marco Hartmann <marco.hartmann@nxp.com>
To:     Marco Hartmann <marco.hartmann@nxp.com>,
        Andy Duan <fugang.duan@nxp.com>,
        "davem@davemloft.net" <davem@davemloft.net>,
        "netdev@vger.kernel.org" <netdev@vger.kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Christian Herber <christian.herber@nxp.com>
Subject: [PATCH net-next 1/1] fec: add C45 MDIO read/write support
Thread-Topic: [PATCH net-next 1/1] fec: add C45 MDIO read/write support
Thread-Index: AQHVVrEbELPNNXpxt0CfMgo+jLB/5Q==
Date:   Mon, 19 Aug 2019 17:11:14 +0000
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References: <1566234659-7164-1-git-send-email-marco.hartmann@nxp.com>
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IEEE 802.3ae clause 45 defines a modified MDIO protocol that uses a two
staged access model in order to increase the address space.

This patch adds support for C45 MDIO read and write accesses, which are
used whenever the MII_ADDR_C45 flag in the regnum argument is set.
In case it is not set, C22 accesses are used as before.

Co-developed-by: Christian Herber <christian.herber@nxp.com>
Signed-off-by: Christian Herber <christian.herber@nxp.com>
Signed-off-by: Marco Hartmann <marco.hartmann@nxp.com>
---
 drivers/net/ethernet/freescale/fec_main.c | 65 +++++++++++++++++++++++++++=
+---
 1 file changed, 59 insertions(+), 6 deletions(-)

diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethern=
et/freescale/fec_main.c
index c01d3ec3e9af..73f8f9a149a1 100644
--- a/drivers/net/ethernet/freescale/fec_main.c
+++ b/drivers/net/ethernet/freescale/fec_main.c
@@ -208,8 +208,11 @@ MODULE_PARM_DESC(macaddr, "FEC Ethernet MAC address");
=20
 /* FEC MII MMFR bits definition */
 #define FEC_MMFR_ST		(1 << 30)
+#define FEC_MMFR_ST_C45		(0)
 #define FEC_MMFR_OP_READ	(2 << 28)
+#define FEC_MMFR_OP_READ_C45	(3 << 28)
 #define FEC_MMFR_OP_WRITE	(1 << 28)
+#define FEC_MMFR_OP_ADDR_WRITE	(0)
 #define FEC_MMFR_PA(v)		((v & 0x1f) << 23)
 #define FEC_MMFR_RA(v)		((v & 0x1f) << 18)
 #define FEC_MMFR_TA		(2 << 16)
@@ -1767,7 +1770,7 @@ static int fec_enet_mdio_read(struct mii_bus *bus, in=
t mii_id, int regnum)
 	struct fec_enet_private *fep =3D bus->priv;
 	struct device *dev =3D &fep->pdev->dev;
 	unsigned long time_left;
-	int ret =3D 0;
+	int ret =3D 0, frame_start, frame_addr, frame_op;
=20
 	ret =3D pm_runtime_get_sync(dev);
 	if (ret < 0)
@@ -1775,9 +1778,36 @@ static int fec_enet_mdio_read(struct mii_bus *bus, i=
nt mii_id, int regnum)
=20
 	reinit_completion(&fep->mdio_done);
=20
+	if (MII_ADDR_C45 & regnum) {
+		frame_start =3D FEC_MMFR_ST_C45;
+
+		/* write address */
+		frame_addr =3D (regnum >> 16);
+		writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
+		       FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
+		       FEC_MMFR_TA | (regnum & 0xFFFF),
+		       fep->hwp + FEC_MII_DATA);
+
+		/* wait for end of transfer */
+		time_left =3D wait_for_completion_timeout(&fep->mdio_done,
+				usecs_to_jiffies(FEC_MII_TIMEOUT));
+		if (time_left =3D=3D 0) {
+			netdev_err(fep->netdev, "MDIO address write timeout\n");
+			ret  =3D -ETIMEDOUT;
+		}
+
+		frame_op =3D FEC_MMFR_OP_READ_C45;
+
+	} else {
+		/* C22 read */
+		frame_op =3D FEC_MMFR_OP_READ;
+		frame_start =3D FEC_MMFR_ST;
+		frame_addr =3D regnum;
+	}
+
 	/* start a read op */
-	writel(FEC_MMFR_ST | FEC_MMFR_OP_READ |
-		FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
+	writel(frame_start | frame_op |
+		FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
 		FEC_MMFR_TA, fep->hwp + FEC_MII_DATA);
=20
 	/* wait for end of transfer */
@@ -1804,7 +1834,7 @@ static int fec_enet_mdio_write(struct mii_bus *bus, i=
nt mii_id, int regnum,
 	struct fec_enet_private *fep =3D bus->priv;
 	struct device *dev =3D &fep->pdev->dev;
 	unsigned long time_left;
-	int ret;
+	int ret, frame_start, frame_addr;
=20
 	ret =3D pm_runtime_get_sync(dev);
 	if (ret < 0)
@@ -1814,9 +1844,32 @@ static int fec_enet_mdio_write(struct mii_bus *bus, =
int mii_id, int regnum,
=20
 	reinit_completion(&fep->mdio_done);
=20
+	if (MII_ADDR_C45 & regnum) {
+		frame_start =3D FEC_MMFR_ST_C45;
+
+		/* write address */
+		frame_addr =3D (regnum >> 16);
+		writel(frame_start | FEC_MMFR_OP_ADDR_WRITE |
+		       FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
+		       FEC_MMFR_TA | (regnum & 0xFFFF),
+		       fep->hwp + FEC_MII_DATA);
+
+		/* wait for end of transfer */
+		time_left =3D wait_for_completion_timeout(&fep->mdio_done,
+			usecs_to_jiffies(FEC_MII_TIMEOUT));
+		if (time_left =3D=3D 0) {
+			netdev_err(fep->netdev, "MDIO address write timeout\n");
+			ret  =3D -ETIMEDOUT;
+		}
+	} else {
+		/* C22 write */
+		frame_start =3D FEC_MMFR_ST;
+		frame_addr =3D regnum;
+	}
+
 	/* start a write op */
-	writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE |
-		FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) |
+	writel(frame_start | FEC_MMFR_OP_WRITE |
+		FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) |
 		FEC_MMFR_TA | FEC_MMFR_DATA(value),
 		fep->hwp + FEC_MII_DATA);
=20
--=20
2.7.4