Received: by 2002:a25:8b12:0:0:0:0:0 with SMTP id i18csp3172009ybl; Mon, 19 Aug 2019 13:30:28 -0700 (PDT) X-Google-Smtp-Source: APXvYqxPn+sb6Oouv3zHLH6R1G08AcMv5KVw9uats8AqoBJxt25i5bVOCh6kH6/79ByNdHQ93iOz X-Received: by 2002:a17:90a:2525:: with SMTP id j34mr23284373pje.11.1566246628753; Mon, 19 Aug 2019 13:30:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566246628; cv=none; d=google.com; s=arc-20160816; b=PkkADqmHawWLl60ebjF7AX1F8Af11XNGchvBrRJz3As9CgU/1/3bWBPeymheh/yVhB eeTVM67nEt6LPiE0SAamwhElxz991jPXysn1vGy85FLTLe8yTkmO+M/8fLlte8dgj5/t vWeUoKNb0o9vLmbKNQyOmPv/P3/FynBGYrC+QpuJToZ+nTuC8CyBIkl2u+ITbxqEoUt1 L4fDqjLQpmBTLItCkr9GXAILsp+Hg+f3F1b89GK3zmjYQGjh0BAxt6phugyMrwg3mpiy Myf73eM/VeEDgXJi1RLkbEB4wyrrKfU8/6PEcUlOsb952rFIhZHSQwW8wqFNnvFnB3Y8 tN4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:dkim-signature:content-transfer-encoding :content-language:in-reply-to:mime-version:user-agent:date :message-id:from:references:cc:to:subject; bh=WyjGFMCx57IDIkIARHgc/p/3DlhW1CTKBnwe7XnjJY8=; b=OJk5GSQdsyLtcOe8xnS3xOsat6jhFneQun2ErnVY1ToF2YFZwqxHv65BvOlNV68X/f dcAuAcDpvHV4sIddJzhP5uwuWm5d2dO7Fk4vCVXKlPtOPNgQL97ZjV87kdh3fOKqWL/c x/x0IK3NlcwOE8WMpz4vjE8zLFkrQNjZWnBAJzu1XC0KyqCq4oysFYh9yWKhjwpJ8Z7W JCd2i3Buz3asyozL0KUmv7Z9+Jpc27vULV5cQqVnSl5KltA1vxpefujAEUkys7oBjDzi Sls+cn6drBmZwRFdRRvf6p4pVtQl0f/Yjh6OvmVRuJ0fdlVIxYN94q0s5MV2YnZSvYWI ixiQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=MWtSopOR; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r8si11056387pfh.185.2019.08.19.13.30.14; Mon, 19 Aug 2019 13:30:28 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@nvidia.com header.s=n1 header.b=MWtSopOR; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728455AbfHSU3V (ORCPT + 99 others); Mon, 19 Aug 2019 16:29:21 -0400 Received: from hqemgate14.nvidia.com ([216.228.121.143]:4862 "EHLO hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727988AbfHSU3S (ORCPT ); Mon, 19 Aug 2019 16:29:18 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Mon, 19 Aug 2019 13:29:17 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Mon, 19 Aug 2019 13:29:18 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Mon, 19 Aug 2019 13:29:18 -0700 Received: from DRHQMAIL107.nvidia.com (10.27.9.16) by HQMAIL101.nvidia.com (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 19 Aug 2019 20:29:17 +0000 Received: from [10.2.167.147] (10.124.1.5) by DRHQMAIL107.nvidia.com (10.27.9.16) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 19 Aug 2019 20:29:16 +0000 Subject: Re: [PATCH 10/14] serial: tegra: add support to use 8 bytes trigger To: Krishna Yarlagadda , , , , , , CC: , , , , "Shardar Shariff Md" References: <1565609303-27000-1-git-send-email-kyarlagadda@nvidia.com> <1565609303-27000-11-git-send-email-kyarlagadda@nvidia.com> From: Jon Hunter Message-ID: Date: Mon, 19 Aug 2019 21:29:15 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <1565609303-27000-11-git-send-email-kyarlagadda@nvidia.com> X-Originating-IP: [10.124.1.5] X-ClientProxiedBy: HQMAIL101.nvidia.com (172.20.187.10) To DRHQMAIL107.nvidia.com (10.27.9.16) Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1566246557; bh=WyjGFMCx57IDIkIARHgc/p/3DlhW1CTKBnwe7XnjJY8=; h=X-PGP-Universal:Subject:To:CC:References:From:Message-ID:Date: User-Agent:MIME-Version:In-Reply-To:X-Originating-IP: X-ClientProxiedBy:Content-Type:Content-Language: Content-Transfer-Encoding; b=MWtSopOR49l87pUtrMYz3a1WgQUITI3/vrtW8PIEM/d5lyR+MgP4+2FviE+v2getX wwB9d+NUWSNlhdaU2fl9UMMKBbvYsVUmUvwx8LZX/J8UIlUXZs9wegKw6spKfCrNTm /j8xTB3QrqedefG4bJivLueowAphXQWodyuHfeCOaL34j1Hc/OuPqDveB+mu0pL8Bg mjhkk8FX0vGA8SjBFN8Op5/wgpFAyU+j3k0suK9tqWDoSSzXht1dSqIrvtG9UjVBi4 tuxb4KWAWcEvJxuNDnumqfJ8oVUVcW0DOPjS2qvwP36OQOh4YNfn/piFxOabaEHYfc uUtxMU13PRwCw== Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/08/2019 12:28, Krishna Yarlagadda wrote: > From: Shardar Shariff Md > > Add support to use 8 bytes trigger for Tegra186 SOC. > > Signed-off-by: Shardar Shariff Md > Signed-off-by: Krishna Yarlagadda > --- > drivers/tty/serial/serial-tegra.c | 13 +++++++++++-- > 1 file changed, 11 insertions(+), 2 deletions(-) > > diff --git a/drivers/tty/serial/serial-tegra.c b/drivers/tty/serial/serial-tegra.c > index 329923c..03d1d20 100644 > --- a/drivers/tty/serial/serial-tegra.c > +++ b/drivers/tty/serial/serial-tegra.c > @@ -88,6 +88,7 @@ struct tegra_uart_chip_data { > bool support_clk_src_div; > bool fifo_mode_enable_status; > int uart_max_port; > + int dma_burst_bytes; I assume that this is a maximum, so why not say max_dma_burst_bytes? > }; > > struct tegra_uart_port { > @@ -933,7 +934,12 @@ static int tegra_uart_hw_init(struct tegra_uart_port *tup) > * programmed in the DMA registers. > */ > tup->fcr_shadow = UART_FCR_ENABLE_FIFO; > - tup->fcr_shadow |= UART_FCR_R_TRIG_01; > + > + if (tup->cdata->dma_burst_bytes == 8) > + tup->fcr_shadow |= UART_FCR_R_TRIG_10; > + else > + tup->fcr_shadow |= UART_FCR_R_TRIG_01; > + > tup->fcr_shadow |= TEGRA_UART_TX_TRIG_16B; > tegra_uart_write(tup, tup->fcr_shadow, UART_FCR); > > @@ -1046,7 +1052,7 @@ static int tegra_uart_dma_channel_allocate(struct tegra_uart_port *tup, > } > dma_sconfig.src_addr = tup->uport.mapbase; > dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; > - dma_sconfig.src_maxburst = 4; > + dma_sconfig.src_maxburst = tup->cdata->dma_burst_bytes; > tup->rx_dma_chan = dma_chan; > tup->rx_dma_buf_virt = dma_buf; > tup->rx_dma_buf_phys = dma_phys; > @@ -1325,6 +1331,7 @@ static struct tegra_uart_chip_data tegra20_uart_chip_data = { > .support_clk_src_div = false, > .fifo_mode_enable_status = false, > .uart_max_port = 5, > + .dma_burst_bytes = 4, Isn't it simpler to store the TRIG value here? Jon -- nvpublic