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received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: 4kHjHkpd75omtldVdFuSGja2GKWeSSEM/JMwZMdcUYwGeEKOEtUryu0Pkq0zwj4MdVyQ0PaifQVDpcUdGi0uljc8pLUcaQttV1A7QIvhHsVGKtwY/whNYFmUjtIMVEPg4A/VqRdCErxN2oq9nUZRG4sR/xtz7sxsaSg9QukmhK6DBzlu6EioYpBz6WTPdAVthQNZQX+oqJQG2JUWQ4cedA7SxTM2zR/ZCg/D7cxzckAAayyErMtu3J9KBDpn4jLDzTVd1nb9Ynv0UsQlSVx3bmarJgsIlHQFNDyNMJpUdBBROjePsLXmEHsw5YgNUKs1e5DhIvw4ogpb1jYrmCS787O88ah8NSDQNZJPW/bEnXfZDaQqgm3DP0XcIMHiimZGwfBkmqIwX07YfSv40n4VxwTs0LCS4+nIsWEAwnMAih8= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0bf59a97-d31a-40d3-c22c-08d725134170 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Aug 2019 02:08:12.7550 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: J6dch3OYrU2FvsnfBlBsSH3pO3IRSuGZz9hLpShT9dHWvRyRpv3HLkCBUpJX5XfdIB6L/lbxy/y3xA7uR3h5Qg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR0402MB2702 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Marco Hartmann Sent: Tuesday, August 20, 2019 1:11 AM > IEEE 802.3ae clause 45 defines a modified MDIO protocol that uses a two > staged access model in order to increase the address space. >=20 > This patch adds support for C45 MDIO read and write accesses, which are > used whenever the MII_ADDR_C45 flag in the regnum argument is set. > In case it is not set, C22 accesses are used as before. >=20 > Co-developed-by: Christian Herber > Signed-off-by: Christian Herber > Signed-off-by: Marco Hartmann > --- > drivers/net/ethernet/freescale/fec_main.c | 65 > ++++++++++++++++++++++++++++--- > 1 file changed, 59 insertions(+), 6 deletions(-) >=20 > diff --git a/drivers/net/ethernet/freescale/fec_main.c > b/drivers/net/ethernet/freescale/fec_main.c > index c01d3ec3e9af..73f8f9a149a1 100644 > --- a/drivers/net/ethernet/freescale/fec_main.c > +++ b/drivers/net/ethernet/freescale/fec_main.c > @@ -208,8 +208,11 @@ MODULE_PARM_DESC(macaddr, "FEC Ethernet > MAC address"); >=20 > /* FEC MII MMFR bits definition */ > #define FEC_MMFR_ST (1 << 30) > +#define FEC_MMFR_ST_C45 (0) > #define FEC_MMFR_OP_READ (2 << 28) > +#define FEC_MMFR_OP_READ_C45 (3 << 28) > #define FEC_MMFR_OP_WRITE (1 << 28) > +#define FEC_MMFR_OP_ADDR_WRITE (0) > #define FEC_MMFR_PA(v) ((v & 0x1f) << 23) > #define FEC_MMFR_RA(v) ((v & 0x1f) << 18) > #define FEC_MMFR_TA (2 << 16) > @@ -1767,7 +1770,7 @@ static int fec_enet_mdio_read(struct mii_bus *bus, > int mii_id, int regnum) > struct fec_enet_private *fep =3D bus->priv; > struct device *dev =3D &fep->pdev->dev; > unsigned long time_left; > - int ret =3D 0; > + int ret =3D 0, frame_start, frame_addr, frame_op; Add bool variable: bool is_c45 =3D !!(regnum & MII_ADDR_C45); >=20 > ret =3D pm_runtime_get_sync(dev); > if (ret < 0) > @@ -1775,9 +1778,36 @@ static int fec_enet_mdio_read(struct mii_bus > *bus, int mii_id, int regnum) >=20 > reinit_completion(&fep->mdio_done); >=20 > + if (MII_ADDR_C45 & regnum) { if (is_c45) > + frame_start =3D FEC_MMFR_ST_C45; > + > + /* write address */ > + frame_addr =3D (regnum >> 16); > + writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | > + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | > + FEC_MMFR_TA | (regnum & 0xFFFF), > + fep->hwp + FEC_MII_DATA); > + > + /* wait for end of transfer */ > + time_left =3D wait_for_completion_timeout(&fep->mdio_done, > + usecs_to_jiffies(FEC_MII_TIMEOUT)); > + if (time_left =3D=3D 0) { > + netdev_err(fep->netdev, "MDIO address write timeout\n"); > + ret =3D -ETIMEDOUT; Should be: goto out; > + } > + > + frame_op =3D FEC_MMFR_OP_READ_C45; > + > + } else { > + /* C22 read */ > + frame_op =3D FEC_MMFR_OP_READ; > + frame_start =3D FEC_MMFR_ST; > + frame_addr =3D regnum; > + } > + > /* start a read op */ > - writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | > - FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | > + writel(frame_start | frame_op | > + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | > FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); >=20 > /* wait for end of transfer */ > @@ -1804,7 +1834,7 @@ static int fec_enet_mdio_write(struct mii_bus *bus, > int mii_id, int regnum, > struct fec_enet_private *fep =3D bus->priv; > struct device *dev =3D &fep->pdev->dev; > unsigned long time_left; > - int ret; > + int ret, frame_start, frame_addr; >=20 > ret =3D pm_runtime_get_sync(dev); > if (ret < 0) > @@ -1814,9 +1844,32 @@ static int fec_enet_mdio_write(struct mii_bus > *bus, int mii_id, int regnum, bool is_c45 =3D !!(regnum & MII_ADDR_C45); >=20 > reinit_completion(&fep->mdio_done); >=20 > + if (MII_ADDR_C45 & regnum) { if (!is_c45) { > + frame_start =3D FEC_MMFR_ST_C45; > + > + /* write address */ > + frame_addr =3D (regnum >> 16); > + writel(frame_start | FEC_MMFR_OP_ADDR_WRITE | > + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | > + FEC_MMFR_TA | (regnum & 0xFFFF), > + fep->hwp + FEC_MII_DATA); > + > + /* wait for end of transfer */ > + time_left =3D wait_for_completion_timeout(&fep->mdio_done, > + usecs_to_jiffies(FEC_MII_TIMEOUT)); > + if (time_left =3D=3D 0) { > + netdev_err(fep->netdev, "MDIO address write timeout\n"); > + ret =3D -ETIMEDOUT; Like mdio read, it should be: goto out;=20 > + } > + } else { > + /* C22 write */ > + frame_start =3D FEC_MMFR_ST; > + frame_addr =3D regnum; > + } > + > /* start a write op */ > - writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | > - FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | > + writel(frame_start | FEC_MMFR_OP_WRITE | > + FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(frame_addr) | > FEC_MMFR_TA | FEC_MMFR_DATA(value), > fep->hwp + FEC_MII_DATA); >=20 > -- > 2.7.4