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From:   "Z.q. Hou" <zhiqiang.hou@nxp.com>
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CC:     "M.h. Lian" <minghuan.lian@nxp.com>,
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Subject: [PATCHv2 2/4] PCI: dwc: Return directly when num-lanes is not found
Thread-Topic: [PATCHv2 2/4] PCI: dwc: Return directly when num-lanes is not
 found
Thread-Index: AQHVVyjoYYapbxP8hUy34gCcDaXGwQ==
Date:   Tue, 20 Aug 2019 07:28:49 +0000
Message-ID: <20190820073022.24217-3-Zhiqiang.Hou@nxp.com>
References: <20190820073022.24217-1-Zhiqiang.Hou@nxp.com>
In-Reply-To: <20190820073022.24217-1-Zhiqiang.Hou@nxp.com>
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From: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

The num-lanes is optional, so probably it isn't added
on some platforms. The subsequent programming is base
on the num-lanes, hence return when it is not found.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
---
V2:
 - No change.

 drivers/pci/controller/dwc/pcie-designware.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con=
troller/dwc/pcie-designware.c
index 7d25102c304c..0a89bfd1636e 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -423,8 +423,10 @@ void dw_pcie_setup(struct dw_pcie *pci)
=20
=20
 	ret =3D of_property_read_u32(np, "num-lanes", &lanes);
-	if (ret)
-		lanes =3D 0;
+	if (ret) {
+		dev_dbg(pci->dev, "property num-lanes isn't found\n");
+		return;
+	}
=20
 	/* Set the number of lanes */
 	val =3D dw_pcie_readl_dbi(pci, PCIE_PORT_LINK_CONTROL);
--=20
2.17.1