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From:   Stefan-gabriel Mirea <stefan-gabriel.mirea@nxp.com>
To:     Shawn Guo <shawnguo@kernel.org>
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        Cosmin Stefan Stoica <cosmin.stoica@nxp.com>,
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Subject: Re: [PATCH v2 3/6] arm64: dts: fsl: Add device tree for S32V234-EVB
Thread-Topic: [PATCH v2 3/6] arm64: dts: fsl: Add device tree for S32V234-EVB
Thread-Index: AQHVV3W1bpUQayLw/Uqx7+IPeeYhYQ==
Date:   Tue, 20 Aug 2019 16:38:34 +0000
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References: <20190809112853.15846-1-stefan-gabriel.mirea@nxp.com>
 <20190809112853.15846-4-stefan-gabriel.mirea@nxp.com>
 <20190819085816.GI5999@X250>
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Hello Shawn,=0A=
=0A=
Thank you for your suggestions!=0A=
=0A=
On 8/19/2019 11:58 AM, Shawn Guo wrote:=0A=
> On Fri, Aug 09, 2019 at 11:29:12AM +0000, Stefan-gabriel Mirea wrote:=0A=
>>  .../boot/dts/freescale/fsl-s32v234-evb.dts    |  24 ++++=0A=
> =0A=
> The 'fsl-' prefix can be saved here, so that we can distinguish three=0A=
> families by starting string: imx??? for i.MX, fsl-??? for LayerScape,=0A=
> and s32??? for S32.=0A=
=0A=
All right, I will remove the prefixes.=0A=
=0A=
>> +     model =3D "Freescale S32V234";=0A=
> =0A=
> The 'model' is usually used in board level DTS to describe the board.=0A=
=0A=
I will delete the 'model' property from fsl-s32v234.dtsi and add a=0A=
suitable one in fsl-s32v234-evb.dts.=0A=
=0A=
>> +             };=0A=
> =0A=
> Please have a newline between nodes.=0A=
> =0A=
>> +             cpu1: cpu@1 {=0A=
=0A=
I've got it.=0A=
=0A=
>> +                             interrupts =3D <0 59 1>;=0A=
> =0A=
> Please use GIC_SPI and IRQ_TYPE_xxx defines to make it more readable.=0A=
=0A=
I will use GIC_SPI/GIC_PPI and IRQ_TYPE_xxx/GIC_CPU_MASK_xxx where=0A=
applicable.=0A=
=0A=
>> +=0A=
>> +     timer {=0A=
>> +             compatible =3D "arm,armv8-timer";=0A=
>> +             interrupts =3D <1 13 0xf08>,=0A=
>> +                          <1 14 0xf08>,=0A=
>> +                          <1 11 0xf08>,=0A=
>> +                          <1 10 0xf08>;=0A=
>> +             /* clock-frequency might be modified by u-boot, depending =
on the=0A=
>> +              * chip version.=0A=
>> +              */=0A=
>> +             clock-frequency =3D <10000000>;=0A=
>> +     };=0A=
>> +=0A=
>> +     gic: interrupt-controller@7d001000 {=0A=
>> +             compatible =3D "arm,cortex-a15-gic", "arm,cortex-a9-gic";=
=0A=
>> +             #interrupt-cells =3D <3>;=0A=
>> +             #address-cells =3D <0>;=0A=
>> +             interrupt-controller;=0A=
>> +             reg =3D <0 0x7d001000 0 0x1000>,=0A=
>> +                   <0 0x7d002000 0 0x2000>,=0A=
>> +                   <0 0x7d004000 0 0x2000>,=0A=
>> +                   <0 0x7d006000 0 0x2000>;=0A=
>> +             interrupts =3D <1 9 0xf04>;=0A=
>> +     };=0A=
> =0A=
> We usually put these core platform devices prior to 'soc' node.=0A=
=0A=
Sure, I will move the 'timer' and 'interrupt-controller' nodes right=0A=
before 'soc'.=0A=
=0A=
Regards,=0A=
Stefan=0A=