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Wang" , "angus@akkea.ca" , "agx@sigxcpu.org" , Anson Huang , Peng Fan , Jacky Bai , Stephen Boyd , "linux-clk@vger.kernel.org" Subject: Re: [PATCH v4] arm64: dts: imx8mq: Init rates and parents configs for clocks Thread-Topic: [PATCH v4] arm64: dts: imx8mq: Init rates and parents configs for clocks Thread-Index: AQHVRVgHX+vi+LJNg0ufd7EEy7KERw== Date: Wed, 21 Aug 2019 20:39:56 +0000 Message-ID: References: <20190728152040.15323-1-daniel.baluta@nxp.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=leonard.crestez@nxp.com; x-originating-ip: [89.37.124.34] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: c61d291f-35ce-4134-8403-08d72677ba18 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0;PCL:0;RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(4618075)(2017052603328)(7193020);SRVR:VI1PR04MB3293; x-ms-traffictypediagnostic: VI1PR04MB3293: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:8882; x-forefront-prvs: 0136C1DDA4 x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(4636009)(346002)(136003)(396003)(39850400004)(376002)(366004)(199004)(189003)(6436002)(7736002)(81166006)(71200400001)(2501003)(305945005)(74316002)(229853002)(25786009)(66066001)(55016002)(71190400001)(9686003)(44832011)(53546011)(6506007)(476003)(2906002)(81156014)(5660300002)(486006)(446003)(14454004)(52536014)(186003)(26005)(8676002)(102836004)(54906003)(99286004)(110136005)(6636002)(76176011)(76116006)(53936002)(7696005)(478600001)(33656002)(8936002)(316002)(7416002)(256004)(4326008)(6116002)(3846002)(86362001)(66446008)(66946007)(6246003)(66476007)(66556008)(64756008)(32563001);DIR:OUT;SFP:1101;SCL:1;SRVR:VI1PR04MB3293;H:VI1PR04MB7023.eurprd04.prod.outlook.com;FPR:;SPF:None;LANG:en;PTR:InfoNoRecords;A:1;MX:1; received-spf: None (protection.outlook.com: nxp.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: Nskwv3f3kHMYD+qYyjlM44//nPkscpkyQf2HIijZvlB3FRv4AAlXpZkzusnzI6heVhwPhd/0uUxguDeiH5i7krvGcB0vfozK2exKcippRg9VAKYrdtnjLce/4hsFBOAmXlJdXzXKYpec43wxMZuh0/mosyBWyssnUmX3g47c8fp5AdUEaVInYJAiwmdIxqUrlqJ+BkOAV0jKIxD/e1so8TV3Uj3JsiSeubqc/bNheClSFwRE4v1hSz8xQlGviQsJMizLp11M991AXDsL24qv1XW4YqYtUP3EvNutcGEW8o0ROw8WEwvDbVf7tU+hcaHodSp6KKMBKcAHoy3vMeaMnkTp9qbn9Cxb4urtkqPT9Wd1SAQ1JNnrwVHGZiYVbYBz5IXO54nMuyg2JortlqEqeXjtuCJTZrskxQWeG1vIdf8= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: c61d291f-35ce-4134-8403-08d72677ba18 X-MS-Exchange-CrossTenant-originalarrivaltime: 21 Aug 2019 20:39:56.0116 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: gluK+HYspweKS2HObGCCufjxR5APrAYLj7DglvaFo2Eyen7OLEseU2vIzXFaE7gar5IOxIe6Bk4x9aklZrD2vA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB3293 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 28.07.2019 18:20, Daniel Baluta wrote:=0A= > From: Abel Vesa =0A= > =0A= > Add the initial configuration for clocks that need default parent and rat= e=0A= > setting. This is based on the vendor tree clock provider parents and rate= s=0A= > configuration except this is doing the setup in dts rather then using clo= ck=0A= > consumer API in a clock provider driver.=0A= > =0A= > Note that by adding the initial rate setting for audio_pll1/audio_pll=0A= > setting we need to remove it from imx8mq-librem5-devkit.dts=0A= =0A= Setting default rates for audio_pll1 and audio_pll2 in soc dtsi makes a =0A= lot of sense to me; the intention is for one to run at a multiple of =0A= 44.1k and another at a multiple of 48k.=0A= =0A= > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/= dts/freescale/imx8mq.dtsi=0A= > index 02fbd0625318..a55d72ba2e05 100644=0A= > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi=0A= > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi=0A= > @@ -494,6 +494,25 @@=0A= > clock-names =3D "ckil", "osc_25m", "osc_27m",=0A= > "clk_ext1", "clk_ext2",=0A= > "clk_ext3", "clk_ext4";=0A= > + assigned-clocks =3D <&clk IMX8MQ_VIDEO_PLL1>,=0A= > + <&clk IMX8MQ_AUDIO_PLL1>,=0A= > + <&clk IMX8MQ_AUDIO_PLL2>,=0A= > + <&clk IMX8MQ_CLK_AHB>,=0A= > + <&clk IMX8MQ_CLK_NAND_USDHC_BUS>,=0A= > + <&clk IMX8MQ_CLK_AUDIO_AHB>,=0A= > + <&clk IMX8MQ_VIDEO_PLL1_REF_SEL>,=0A= > + <&clk IMX8MQ_CLK_NOC>;=0A= > + assigned-clock-parents =3D <0>,=0A= > + <0>,=0A= > + <0> > + <&clk IMX8MQ_SYS1_PLL_133M>,=0A= > + <&clk IMX8MQ_SYS1_PLL_266M>,=0A= > + <&clk IMX8MQ_SYS2_PLL_500M>,=0A= > + <&clk IMX8MQ_CLK_27M>,=0A= > + <&clk IMX8MQ_SYS1_PLL_800M>;=0A= > + assigned-clock-rates =3D <593999999>,=0A= > + <786432000>,=0A= > + <722534400>;=0A= =0A= The audio PLLs should run below 650 mHz so please use 393216000 and =0A= 361267200 instead of 786432000 and 722534400. For the 8mm equivalent see = =0A= commit 053a4ffe2988 ("clk: imx: imx8mm: fix audio pll setting").=0A= =0A= You should also move the unbypassing of AUDIO_PLL1 and AUDIO_PLL2 here =0A= just add two more assigned-clocks and assigned-clock-parents.=0A= =0A= --=0A= Regards,=0A= Leonard=0A=