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From:   "Ghannam, Yazen" <Yazen.Ghannam@amd.com>
To:     "linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>
CC:     "Ghannam, Yazen" <Yazen.Ghannam@amd.com>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        "bp@alien8.de" <bp@alien8.de>
Subject: [PATCH v3 2/8] EDAC/amd64: Recognize DRAM device type with
 EDAC_CTL_CAP
Thread-Topic: [PATCH v3 2/8] EDAC/amd64: Recognize DRAM device type with
 EDAC_CTL_CAP
Thread-Index: AQHVWHyImxX6rEh2Ukm1sm9yHR4aIQ==
Date:   Wed, 21 Aug 2019 23:59:56 +0000
Message-ID: <20190821235938.118710-3-Yazen.Ghannam@amd.com>
References: <20190821235938.118710-1-Yazen.Ghannam@amd.com>
In-Reply-To: <20190821235938.118710-1-Yazen.Ghannam@amd.com>
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From: Yazen Ghannam <yazen.ghannam@amd.com>

AMD Family 17h systems support x4 and x16 DRAM devices. However, the
device type is not checked when setting EDAC_CTL_CAP.

Set the appropriate EDAC_CTL_CAP flag based on the device type.

Default to x8 DRAM device when neither the x4 or x16 bits are set.

Fixes: 2d09d8f301f5 ("EDAC, amd64: Determine EDAC MC capabilities on Fam17h=
")
Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
Link:
https://lkml.kernel.org/r/20190709215643.171078-3-Yazen.Ghannam@amd.com

v2->v3:
* Add case for x8 DRAM devices.

v1->v2:
* No change.

 drivers/edac/amd64_edac.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index dd60cf5a3d96..0e8b2137edbb 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -3150,12 +3150,15 @@ static bool ecc_enabled(struct pci_dev *F3, u16 nid=
)
 static inline void
 f17h_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pv=
t)
 {
-	u8 i, ecc_en =3D 1, cpk_en =3D 1;
+	u8 i, ecc_en =3D 1, cpk_en =3D 1, dev_x4 =3D 1, dev_x16 =3D 1;
=20
 	for_each_umc(i) {
 		if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) {
 			ecc_en &=3D !!(pvt->umc[i].umc_cap_hi & UMC_ECC_ENABLED);
 			cpk_en &=3D !!(pvt->umc[i].umc_cap_hi & UMC_ECC_CHIPKILL_CAP);
+
+			dev_x4 &=3D !!(pvt->umc[i].dimm_cfg & BIT(6));
+			dev_x16 &=3D !!(pvt->umc[i].dimm_cfg & BIT(7));
 		}
 	}
=20
@@ -3163,8 +3166,14 @@ f17h_determine_edac_ctl_cap(struct mem_ctl_info *mci=
, struct amd64_pvt *pvt)
 	if (ecc_en) {
 		mci->edac_ctl_cap |=3D EDAC_FLAG_SECDED;
=20
-		if (cpk_en)
-			mci->edac_ctl_cap |=3D EDAC_FLAG_S4ECD4ED;
+		if (cpk_en) {
+			if (dev_x4)
+				mci->edac_ctl_cap |=3D EDAC_FLAG_S4ECD4ED;
+			else if (dev_x16)
+				mci->edac_ctl_cap |=3D EDAC_FLAG_S16ECD16ED;
+			else
+				mci->edac_ctl_cap |=3D EDAC_FLAG_S8ECD8ED;
+		}
 	}
 }
=20
--=20
2.17.1