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From:   Mathieu Poirier <mathieu.poirier@linaro.org>
To:     yabinc@google.com, suzuki.poulose@arm.com, leo.yan@linaro.org
Cc:     mike.leach@arm.com, alexander.shishkin@linux.intel.com,
        linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: [PATCH 0/2] coresight: Add barrier packet when moving offset forward
Date:   Thu, 22 Aug 2019 16:09:13 -0600
Message-Id: <20190822220915.8876-1-mathieu.poirier@linaro.org>
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk

Hi Yabin,

When doing more tests on your patch that adjust the offset to fit the  
available space in the perf ring buffer[1], I noticed the decoder wasn't
able to decode the traces that had been collected.  The issue was observed
in CPU wide scenarios but I also suspect they would have showed up in
per-thread mode given the right conditions.

I traced the problem to the moving forward of the offset in the trace
buffer.  Doing so skips over the barrier packets originally inserted in
function tmc_sync_etr_buf(), which in turn prevents the decoder from
properly synchronising with the trace packets.

I fixed the condition by inserting barrier packets once the offset has been
moved forward, making sure that alignment rules are respected.

I'd be grateful if you could review and test my changes to make sure things
still work on your side.

Applies cleanly on the coresight next branch.

Best regards,
Mathieu 

[1]. https://lkml.org/lkml/2019/8/14/1336


Mathieu Poirier (2):
  coresight: tmc: Make memory width mask computation into a function
  coresight: tmc-etr: Add barrier packet when moving offset forward

 .../hwtracing/coresight/coresight-tmc-etf.c   | 23 +---------
 .../hwtracing/coresight/coresight-tmc-etr.c   | 43 ++++++++++++++-----
 drivers/hwtracing/coresight/coresight-tmc.c   | 28 ++++++++++++
 drivers/hwtracing/coresight/coresight-tmc.h   |  1 +
 4 files changed, 64 insertions(+), 31 deletions(-)

-- 
2.17.1