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From:   Fancy Fang <chen.fang@nxp.com>
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Subject: [PATCH 1/2] ARM: dts: imx7ulp: remove mipi pll clock node
Thread-Topic: [PATCH 1/2] ARM: dts: imx7ulp: remove mipi pll clock node
Thread-Index: AQHVWUryVFTPKJmy3EOKbGcFK1cgTg==
Date:   Fri, 23 Aug 2019 00:37:30 +0000
Message-ID: <20190823003600.8317-1-chen.fang@nxp.com>
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According to the IMX7ULP reference manual, the mipi pll
clock comes from the MIPI PHY PLL output. So it should
not be defined as a fixed clock. So remove this clock
node and all the references to it.

Signed-off-by: Fancy Fang <chen.fang@nxp.com>
---
 arch/arm/boot/dts/imx7ulp.dtsi | 17 ++++-------------
 1 file changed, 4 insertions(+), 13 deletions(-)

diff --git a/arch/arm/boot/dts/imx7ulp.dtsi b/arch/arm/boot/dts/imx7ulp.dts=
i
index 6859a3a83750..a7e4004bf428 100644
--- a/arch/arm/boot/dts/imx7ulp.dtsi
+++ b/arch/arm/boot/dts/imx7ulp.dtsi
@@ -87,13 +87,6 @@
 		#clock-cells =3D <0>;
 	};
=20
-	mpll: clock-mpll {
-		compatible =3D "fixed-clock";
-		clock-frequency =3D <480000000>;
-		clock-output-names =3D "mpll";
-		#clock-cells =3D <0>;
-	};
-
 	ahbbridge0: bus@40000000 {
 		compatible =3D "simple-bus";
 		#address-cells =3D <1>;
@@ -258,9 +251,9 @@
 			compatible =3D "fsl,imx7ulp-scg1";
 			reg =3D <0x403e0000 0x10000>;
 			clocks =3D <&rosc>, <&sosc>, <&sirc>,
-				 <&firc>, <&upll>, <&mpll>;
+				 <&firc>, <&upll>;
 			clock-names =3D "rosc", "sosc", "sirc",
-				      "firc", "upll", "mpll";
+				      "firc", "upll";
 			#clock-cells =3D <1>;
 		};
=20
@@ -276,13 +269,12 @@
 				 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
 				 <&scg1 IMX7ULP_CLK_UPLL>,
 				 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
-				 <&scg1 IMX7ULP_CLK_MIPI_PLL>,
 				 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
 				 <&scg1 IMX7ULP_CLK_ROSC>,
 				 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
 			clock-names =3D "nic1_bus_clk", "nic1_clk", "ddr_clk",
 				      "apll_pfd2", "apll_pfd1", "apll_pfd0",
-				      "upll", "sosc_bus_clk", "mpll",
+				      "upll", "sosc_bus_clk",
 				      "firc_bus_clk", "rosc", "spll_bus_clk";
 			assigned-clocks =3D <&pcc2 IMX7ULP_CLK_LPTPM5>;
 			assigned-clock-parents =3D <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
@@ -309,13 +301,12 @@
 				 <&scg1 IMX7ULP_CLK_APLL_PFD0>,
 				 <&scg1 IMX7ULP_CLK_UPLL>,
 				 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
-				 <&scg1 IMX7ULP_CLK_MIPI_PLL>,
 				 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
 				 <&scg1 IMX7ULP_CLK_ROSC>,
 				 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
 			clock-names =3D "nic1_bus_clk", "nic1_clk", "ddr_clk",
 				      "apll_pfd2", "apll_pfd1", "apll_pfd0",
-				      "upll", "sosc_bus_clk", "mpll",
+				      "upll", "sosc_bus_clk",
 				      "firc_bus_clk", "rosc", "spll_bus_clk";
 		};
 	};
--=20
2.17.1