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From:   Paul Burton <paul.burton@mips.com>
To:     Martin Blumenstingl <martin.blumenstingl@googlemail.com>
CC:     "linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
        "john@phrozen.org" <john@phrozen.org>,
        "kishon@ti.com" <kishon@ti.com>,
        Paul Burton <pburton@wavecomp.com>,
        "ralf@linux-mips.org" <ralf@linux-mips.org>,
        "robh+dt@kernel.org" <robh+dt@kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
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        "mark.rutland@arm.com" <mark.rutland@arm.com>,
        "ms@dev.tdt.de" <ms@dev.tdt.de>,
        Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
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Subject: Re: [PATCH v3 4/4] MIPS: lantiq: update the clock alias' for the
 mainline  PCIe PHY driver
Thread-Topic: [PATCH v3 4/4] MIPS: lantiq: update the clock alias' for the
 mainline  PCIe PHY driver
Thread-Index: AQHVWoYpxj9W4cGayUKjpXZeJ7OkUw==
Date:   Sat, 24 Aug 2019 14:13:54 +0000
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References: <20190727120415.15859-5-martin.blumenstingl@googlemail.com>
In-Reply-To: <20190727120415.15859-5-martin.blumenstingl@googlemail.com>
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Hello,

Martin Blumenstingl wrote:
> The mainline PCIe PHY driver has it's own devicetree node. Update the
> clock alias so the mainline driver finds the clocks.
>=20
> The first PCIe PHY is located at 0x1f106800 and exists on VRX200, ARX300
> and GRX390.
> The second PCIe PHY is located at 0x1f700400 and exists on ARX300 and
> GRX390.
> The third PCIe PHY is located at 0x1f106a00 and exists onl on GRX390.
> Lantiq's board support package (called "UGW") names these registers
> "PDI".

Applied to mips-next.

> commit ed90302be64a
> https://git.kernel.org/mips/c/ed90302be64a
>=20
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> Signed-off-by: Paul Burton <paul.burton@mips.com>

Thanks,
    Paul

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