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[209.132.180.67]) by mx.google.com with ESMTP id bb21si6898840pjb.37.2019.08.25.03.45.07; Sun, 25 Aug 2019 03:45:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=microchip.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727130AbfHYKoS (ORCPT + 99 others); Sun, 25 Aug 2019 06:44:18 -0400 Received: from esa2.microchip.iphmx.com ([68.232.149.84]:52882 "EHLO esa2.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726564AbfHYKoS (ORCPT ); Sun, 25 Aug 2019 06:44:18 -0400 Received-SPF: Pass (esa2.microchip.iphmx.com: domain of Horatiu.Vultur@microchip.com designates 198.175.253.82 as permitted sender) identity=mailfrom; client-ip=198.175.253.82; receiver=esa2.microchip.iphmx.com; envelope-from="Horatiu.Vultur@microchip.com"; x-sender="Horatiu.Vultur@microchip.com"; x-conformance=spf_only; x-record-type="v=spf1"; x-record-text="v=spf1 mx a:ushub1.microchip.com a:smtpout.microchip.com a:mx1.microchip.iphmx.com a:mx2.microchip.iphmx.com include:servers.mcsv.net include:mktomail.com include:spf.protection.outlook.com ~all" Received-SPF: None (esa2.microchip.iphmx.com: no sender authenticity information available from domain of postmaster@email.microchip.com) identity=helo; client-ip=198.175.253.82; receiver=esa2.microchip.iphmx.com; envelope-from="Horatiu.Vultur@microchip.com"; x-sender="postmaster@email.microchip.com"; x-conformance=spf_only Authentication-Results: esa2.microchip.iphmx.com; dkim=none (message not signed) header.i=none; spf=Pass smtp.mailfrom=Horatiu.Vultur@microchip.com; spf=None smtp.helo=postmaster@email.microchip.com; dmarc=pass (p=none dis=none) d=microchip.com IronPort-SDR: KPowbCFFfu7Y3KlmeQGDPM/RyuZmKwIUCA3+Aqoii0ObaQkphb31QOYaiWau7lTfXeXuuBBC/3 BWCXEUw2oRbY1EXQq4ArsHGYog9IzfPFzgMUMmxuBC1GaCK0E2TYjpw5zihVfG0AY4fCj6BXhs 9x8QtiAg2EuczCeBrAiFfBlxUlaFwXlZeNAXbSfkACVrpiv6aTD1qcsxJUpUF97oteAAbtq82W aBQR1k/lUF1O0YGOwkZRw1Ktq7DIy6Z+NJ7oR3WYn1Msc5bBbz1Xgj+stRKzoDAgv/4sseW+T2 sRg= X-IronPort-AV: E=Sophos;i="5.64,429,1559545200"; d="scan'208";a="46440873" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 25 Aug 2019 03:44:16 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1713.5; Sun, 25 Aug 2019 03:44:16 -0700 Received: from localhost (10.10.85.251) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.1713.5 via Frontend Transport; Sun, 25 Aug 2019 03:44:15 -0700 Date: Sun, 25 Aug 2019 12:44:15 +0200 From: Horatiu Vultur To: Florian Fainelli CC: Andrew Lunn , , , , , , , , , Subject: Re: [PATCH 1/3] net: Add HW_BRIDGE offload feature Message-ID: <20190825104413.ftnarx46hhym632w@soft-dev3.microsemi.net> References: <1566500850-6247-1-git-send-email-horatiu.vultur@microchip.com> <1566500850-6247-2-git-send-email-horatiu.vultur@microchip.com> <20190822200817.GD21295@lunn.ch> <20190823123929.ta4ikozz7jwkwbo2@soft-dev3.microsemi.net> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline In-Reply-To: User-Agent: NeoMutt/20180716 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The 08/23/2019 16:30, Florian Fainelli wrote: > External E-Mail > > > On 8/23/19 5:39 AM, Horatiu Vultur wrote: > > The 08/22/2019 22:08, Andrew Lunn wrote: > >> External E-Mail > >> > >> > >>> +/* Determin if the SW bridge can be offloaded to HW. Return true if all > >>> + * the interfaces of the bridge have the feature NETIF_F_HW_SWITCHDEV set > >>> + * and have the same netdev_ops. > >>> + */ > >> > >> Hi Horatiu > >> > >> Why do you need these restrictions. The HW bridge should be able to > >> learn that a destination MAC address can be reached via the SW > >> bridge. The software bridge can then forward it out the correct > >> interface. > >> > >> Or are you saying your hardware cannot learn from frames which come > >> from the CPU? > >> > >> Andrew > >> > > Hi Andrew, > > > > I do not believe that our HW can learn from frames which comes from the > > CPU, at least not in the way they are injected today. But in case of Ocelot > > (and the next chip we are working on), we have other issues in mixing with > > foreign interfaces which is why we have the check in > > ocelot_netdevice_dev_check. > > > > More important, as we responded to Nikolay, we properly introduced this > > restriction for the wrong reasons. > > > > In SW bridge I will remove all these restrictions and only set ports in > > promisc mode only if NETIF_F_HW_BRIDGE is not set. > > Then in the network driver I can see if a foreign interface is added to > > the bridge, and when that happens I can set the port in promisc mode. > > Then the frames will be flooded to the SW bridge which eventually will > > send to the foreign interface. > > Is that really necessary? From what I see, it seems to be necessary. > Is not the skb->fwd_offload_mark as well as > the phys_switch_id supposed to tell that information to the bridge already? Yes, the bridge is using the fwd_offload_mark to know that it should or should not forward the frame. But in case that the network driver knows that the SW bridge will not do anything with the frame, then there is no point to send the frame to SW bridge just to use CPU cycles for dropping the frame. > -- > Florian -- /Horatiu