Received: by 2002:a25:8b12:0:0:0:0:0 with SMTP id i18csp3812569ybl;
        Mon, 26 Aug 2019 00:34:28 -0700 (PDT)
X-Google-Smtp-Source: APXvYqzgv+yWEVOAOaMiAWiEAxieRy16t5x7HVpJLUJUVQc02dTmSYVx8bnuMliru3vZgUFr8Tsl
X-Received: by 2002:a63:724f:: with SMTP id c15mr15515843pgn.257.1566804868588;
        Mon, 26 Aug 2019 00:34:28 -0700 (PDT)
ARC-Seal: i=1; a=rsa-sha256; t=1566804868; cv=none;
        d=google.com; s=arc-20160816;
        b=TSiiPjHDy6HFhGqmh18GLWUAMi8e3XOUHnuWk6wW23NCZOkHqCc4mTJFRnRYdotqWx
         L6ANy2+LIvTPj0VhnEe1FzxNHjo+zJYkOmtBYcnL4A5JmnpsM4UViT8rXrZd4ExTXYBo
         e9R8BI0x5DKfujiM5GdW1TQkyNp8C0FINI+uS/t5zmbZN0S70Yo6BAK8rwd7dJYO20dS
         HWJKK9og7IehVi9qxkCYfCEoKOnbAWtnNMohDI+Dlzqmr24sWjIOAnkqdVfLq6nafxgc
         ZVSzmtWVTOSobzhVpGaIz3ITxtZIDs8noc7zjhclhmPhYvjuXvfwYKkex9KPU1ycNCen
         Q5sQ==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816;
        h=list-id:precedence:sender:dkim-signature:mime-version:references
         :in-reply-to:message-id:date:subject:cc:to:from;
        bh=jVsQ77MHmcaFLC4s0eTgGVoxDo/A2MJu8aiRKpUsI/Q=;
        b=IbMJPX4H6SdTS5e7Oe3KfKKLjIE7JdTzaWt90aEbewN1O4V+R1n9pY83OXWMkJ8h5e
         cjw1yT+m5bQui2m/fCPCsLeH0HrlZbrIp1Kiu9GK/5Tm/eNPaDEzF4oijOJM52eFkli0
         6sr0ouiLeQmW+hmXNV3LdCANrVx/Bv83Yrfu5Uex3YP4PJ/H+z+tUKg+txvIB3h54GbR
         JcI2R7LAjtSfDO110xy7d9FZyH6lBD/Jb5A3EFCQJzuW/QAeGOMvW60THpnioOPzGqvZ
         0t+aKwPRkPoJ5aek2n1uXRsI6EOTkyBlDbAN3aSIuH2NEa8opAvHTq4Sxx2q9S+Jz4i5
         qTtg==
ARC-Authentication-Results: i=1; mx.google.com;
       dkim=pass header.i=@nvidia.com header.s=n1 header.b=BX88ouuc;
       spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
       dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com
Return-Path: <linux-kernel-owner@vger.kernel.org>
Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67])
        by mx.google.com with ESMTP id r17si8383994pgo.125.2019.08.26.00.34.12;
        Mon, 26 Aug 2019 00:34:28 -0700 (PDT)
Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Authentication-Results: mx.google.com;
       dkim=pass header.i=@nvidia.com header.s=n1 header.b=BX88ouuc;
       spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
       dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
        id S1730192AbfHZHb7 (ORCPT <rfc822;austinkernel.kim@gmail.com>
        + 99 others); Mon, 26 Aug 2019 03:31:59 -0400
Received: from hqemgate15.nvidia.com ([216.228.121.64]:1300 "EHLO
        hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
        with ESMTP id S1730144AbfHZHb6 (ORCPT
        <rfc822;linux-kernel@vger.kernel.org>);
        Mon, 26 Aug 2019 03:31:58 -0400
Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate15.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA)
        id <B5d638aee0000>; Mon, 26 Aug 2019 00:31:59 -0700
Received: from hqmail.nvidia.com ([172.20.161.6])
  by hqpgpgate101.nvidia.com (PGP Universal service);
  Mon, 26 Aug 2019 00:31:57 -0700
X-PGP-Universal: processed;
        by hqpgpgate101.nvidia.com on Mon, 26 Aug 2019 00:31:57 -0700
Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL107.nvidia.com
 (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 26 Aug
 2019 07:31:57 +0000
Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL109.nvidia.com
 (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 26 Aug
 2019 07:31:56 +0000
Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL111.nvidia.com
 (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend
 Transport; Mon, 26 Aug 2019 07:31:56 +0000
Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121)
        id <B5d638ae80001>; Mon, 26 Aug 2019 00:31:56 -0700
From:   Vidya Sagar <vidyas@nvidia.com>
To:     <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
        <robh+dt@kernel.org>, <thierry.reding@gmail.com>,
        <jonathanh@nvidia.com>
CC:     <kishon@ti.com>, <gustavo.pimentel@synopsys.com>,
        <digetx@gmail.com>, <mperttunen@nvidia.com>,
        <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
        <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>, <kthota@nvidia.com>,
        <mmaddireddy@nvidia.com>, <vidyas@nvidia.com>, <sagar.tv@gmail.com>
Subject: [PATCH 1/6] dt-bindings: PCI: tegra: Add sideband pins configuration entries
Date:   Mon, 26 Aug 2019 13:01:38 +0530
Message-ID: <20190826073143.4582-2-vidyas@nvidia.com>
X-Mailer: git-send-email 2.17.1
In-Reply-To: <20190826073143.4582-1-vidyas@nvidia.com>
References: <20190826073143.4582-1-vidyas@nvidia.com>
X-NVConfidentiality: public
MIME-Version: 1.0
Content-Type: text/plain
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;
        t=1566804719; bh=jVsQ77MHmcaFLC4s0eTgGVoxDo/A2MJu8aiRKpUsI/Q=;
        h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer:
         In-Reply-To:References:X-NVConfidentiality:MIME-Version:
         Content-Type;
        b=BX88ouucSggVa8KCQO3Bl2bAB0tI6aUNO8erv2/5t72+dQwwHKdtdWaqFUdD/1zg5
         CoDuzH3Oso0hnDZQxNZdHvdpdr4L8AQqOvz6FXb2E9TTEc4V/9cngOw4T1KqHssbM3
         oGbgV16zaIn2Z3FxedxDHRGHPmlu1kmZAtbTrfwKbTck0uF9ZcT0PBgn8wmUfqB71X
         X9T6EnNHrCjT0s9r6+5NJZ6RRj2UGVHXdmlqmMK+hZcASoDJoyBrhmmunmU+5KoCJc
         o9m3zcAChdZjLfHhzCEL2sKND/q5fadD5Hj+KQbj95rpjccyvISnOi8NDJG7g8oKTM
         8+KImlUGtrkCw==
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

Add optional bindings "pinctrl-names" and "pinctrl-0" to describe pin
configuration information of a particular PCIe controller.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
 .../devicetree/bindings/pci/nvidia,tegra194-pcie.txt      | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
index 674e5adb2895..0ac1b867ac24 100644
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
@@ -83,6 +83,11 @@ Required properties:
 - vddio-pex-ctl-supply: Regulator supply for PCIe side band signals
 
 Optional properties:
+- pinctrl-names: A list of pinctrl state names.
+  It is mandatory for C5 controller and optional for other controllers.
+  - "default": Configures PCIe I/O for proper operation.
+- pinctrl-0: phandle for the 'default' state of pin configuration.
+  It is mandatory for C5 controller and optional for other controllers.
 - supports-clkreq: Refer to Documentation/devicetree/bindings/pci/pci.txt
 - nvidia,update-fc-fixup: This is a boolean property and needs to be present to
     improve performance when a platform is designed in such a way that it
@@ -120,6 +125,9 @@ Tegra194:
 		num-lanes = <8>;
 		linux,pci-domain = <0>;
 
+		pinctrl-names = "default";
+		pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
+
 		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
 		clock-names = "core";
 
-- 
2.17.1