Received: by 2002:a25:8b12:0:0:0:0:0 with SMTP id i18csp3861634ybl;
        Mon, 26 Aug 2019 01:33:15 -0700 (PDT)
X-Google-Smtp-Source: APXvYqwPZ1ErKXmQEqFxHodY7ut4Dg9QyJKzMDpD4PMcXm1xC12WQ4/8Nj47dE0oqQA0asvG4ghq
X-Received: by 2002:a17:90a:de11:: with SMTP id m17mr8345577pjv.38.1566808395604;
        Mon, 26 Aug 2019 01:33:15 -0700 (PDT)
ARC-Seal: i=1; a=rsa-sha256; t=1566808395; cv=none;
        d=google.com; s=arc-20160816;
        b=cenSuX7m+Jw2VvACag/qGusKtEO6TsFtC98CNis/elnjKJvNhSRw2/UJWyctuSkY3t
         OdEJYsrR7GCUoL5y+uhaON22ahM4B4+0JH5Oh47MhqMR9HhheolT0HeFURd9i3W474/T
         +T+Y2x4D56+2hwDRgvR8cg/yRABlouZs/u4nmj4a4Ky/Bo/p3lmxSy8OADjTQacfm+Pk
         pMRqpv2xsIe7srCsFMMQS1aDbFDJIsHw2uu3Rme8kSfwAK+Je4/WT6V9BLBOx3Y88LQ8
         AdrnlG8gh0SiUir1RGz6ZYPyOzuzXoUDJIVVz8D84qbH1NsDpEBGfKdsVhm83WoTIYTS
         9crw==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816;
        h=list-id:precedence:sender:dkim-signature:mime-version:references
         :in-reply-to:message-id:date:subject:cc:to:from;
        bh=haHXWsGgD8MESPMvbZs2yQ/SLeRmS1gQyc9LUmqIL08=;
        b=yBPJp/5CVwiaR1Cej3vX/FJdp1caeek58LiX5Nt4Nv4RkDaUSVo4KNFZ15d8xbBLCb
         cA7dCSJMk5EfPXAjqq0UIHX6QPK6cbnXtp4O/cCS5ImmCvnrpucWBntJXnemtt5GMljU
         AMWhxVNJTcifE2liI7xe7OXSSYZZgKMwdZQ+Xt8k1+JqinRw7oD6e8Liy15v/rMlydE2
         cvn3Qy7q32HvSd7oxRxnDvFMIepleJC+ZTENpeek4D34WZzhOA7SA312uyE42koNaGhe
         If2HPKHFoVPjxu5z/XM/Jo9tnxcVc0q/XMgQaQiOY0AzFXNlkznG7c/JRhEjlYTUIHLZ
         PP4A==
ARC-Authentication-Results: i=1; mx.google.com;
       dkim=pass header.i=@nvidia.com header.s=n1 header.b=enioegNB;
       spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
       dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com
Return-Path: <linux-kernel-owner@vger.kernel.org>
Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67])
        by mx.google.com with ESMTP id g17si8382461pgd.357.2019.08.26.01.32.59;
        Mon, 26 Aug 2019 01:33:15 -0700 (PDT)
Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Authentication-Results: mx.google.com;
       dkim=pass header.i=@nvidia.com header.s=n1 header.b=enioegNB;
       spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
       dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nvidia.com
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
        id S1730205AbfHZHcE (ORCPT <rfc822;austinkernel.kim@gmail.com>
        + 99 others); Mon, 26 Aug 2019 03:32:04 -0400
Received: from hqemgate14.nvidia.com ([216.228.121.143]:19142 "EHLO
        hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
        with ESMTP id S1730006AbfHZHcD (ORCPT
        <rfc822;linux-kernel@vger.kernel.org>);
        Mon, 26 Aug 2019 03:32:03 -0400
Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA)
        id <B5d638af30001>; Mon, 26 Aug 2019 00:32:03 -0700
Received: from hqmail.nvidia.com ([172.20.161.6])
  by hqpgpgate101.nvidia.com (PGP Universal service);
  Mon, 26 Aug 2019 00:32:02 -0700
X-PGP-Universal: processed;
        by hqpgpgate101.nvidia.com on Mon, 26 Aug 2019 00:32:02 -0700
Received: from HQMAIL109.nvidia.com (172.20.187.15) by HQMAIL107.nvidia.com
 (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 26 Aug
 2019 07:32:02 +0000
Received: from HQMAIL101.nvidia.com (172.20.187.10) by HQMAIL109.nvidia.com
 (172.20.187.15) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Mon, 26 Aug
 2019 07:32:02 +0000
Received: from hqnvemgw01.nvidia.com (172.20.150.20) by HQMAIL101.nvidia.com
 (172.20.187.10) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend
 Transport; Mon, 26 Aug 2019 07:32:02 +0000
Received: from vidyas-desktop.nvidia.com (Not Verified[10.24.37.38]) by hqnvemgw01.nvidia.com with Trustwave SEG (v7,5,8,10121)
        id <B5d638aed0000>; Mon, 26 Aug 2019 00:32:01 -0700
From:   Vidya Sagar <vidyas@nvidia.com>
To:     <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
        <robh+dt@kernel.org>, <thierry.reding@gmail.com>,
        <jonathanh@nvidia.com>
CC:     <kishon@ti.com>, <gustavo.pimentel@synopsys.com>,
        <digetx@gmail.com>, <mperttunen@nvidia.com>,
        <linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
        <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>, <kthota@nvidia.com>,
        <mmaddireddy@nvidia.com>, <vidyas@nvidia.com>, <sagar.tv@gmail.com>
Subject: [PATCH 2/6] arm64: tegra: Add configuration for PCIe C5 sideband signals
Date:   Mon, 26 Aug 2019 13:01:39 +0530
Message-ID: <20190826073143.4582-3-vidyas@nvidia.com>
X-Mailer: git-send-email 2.17.1
In-Reply-To: <20190826073143.4582-1-vidyas@nvidia.com>
References: <20190826073143.4582-1-vidyas@nvidia.com>
X-NVConfidentiality: public
MIME-Version: 1.0
Content-Type: text/plain
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;
        t=1566804723; bh=haHXWsGgD8MESPMvbZs2yQ/SLeRmS1gQyc9LUmqIL08=;
        h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer:
         In-Reply-To:References:X-NVConfidentiality:MIME-Version:
         Content-Type;
        b=enioegNBwGCOT2yISiZYdP1kIxO403F96JdyOLm+PfeeD3pmboxHreNCa+wwGs0B7
         YDD44xpHZapFBDlc+d6XPMfhP0HHtGmhSQ2npgdVa68WHSkm3MyyqZTizkBM5+RiXk
         f3vN2TtLI19NHMR0KyWX2FKvgINcR96LeMJxjrrpqmsWwCDkbtJ+J30kK9jyROEKAL
         fFqPyH+3L9RpcA82qr/8FBEV0OVvV/rYizx3q4PW++BtSVylBp0ZcJ7PMLxiM6vkk2
         7BXBz0Zf0xlCgaznTMpWDzZiWxgBEH+fug4pZxwc3Up7ROGxGVHFreUavdFf8fNrG3
         33dUVIDvUQFjQ==
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

Add support to configure PCIe C5's sideband signals PERST# and CLKREQ#
as output and bi-directional signals respectively which unlike other
PCIe controllers sideband signals are not configured by default.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra194.dtsi | 38 +++++++++++++++++++++++-
 1 file changed, 37 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index adebbbf36bd0..3c0cf54f0aab 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -3,8 +3,9 @@
 #include <dt-bindings/gpio/tegra194-gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/mailbox/tegra186-hsp.h>
-#include <dt-bindings/reset/tegra194-reset.h>
+#include <dt-bindings/pinctrl/pinctrl-tegra.h>
 #include <dt-bindings/power/tegra194-powergate.h>
+#include <dt-bindings/reset/tegra194-reset.h>
 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
 
 / {
@@ -130,6 +131,38 @@
 			};
 		};
 
+		pinmux: pinmux@2430000 {
+			compatible = "nvidia,tegra194-pinmux";
+			reg = <0x2430000 0x17000
+			       0xc300000 0x4000>;
+
+			status = "okay";
+
+			pex_rst_c5_out_state: pex_rst_c5_out {
+				pex_rst {
+					nvidia,pins = "pex_l5_rst_n_pgg1";
+					nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+					nvidia,lpdr = <TEGRA_PIN_ENABLE>;
+					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
+					nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				};
+			};
+
+			clkreq_c5_bi_dir_state: clkreq_c5_bi_dir {
+				clkreq {
+					nvidia,pins = "pex_l5_clkreq_n_pgg0";
+					nvidia,schmitt = <TEGRA_PIN_DISABLE>;
+					nvidia,lpdr = <TEGRA_PIN_ENABLE>;
+					nvidia,enable-input = <TEGRA_PIN_ENABLE>;
+					nvidia,io-high-voltage = <TEGRA_PIN_ENABLE>;
+					nvidia,tristate = <TEGRA_PIN_DISABLE>;
+					nvidia,pull = <TEGRA_PIN_PULL_NONE>;
+				};
+			};
+		};
+
 		uarta: serial@3100000 {
 			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 			reg = <0x03100000 0x40>;
@@ -1365,6 +1398,9 @@
 		num-viewport = <8>;
 		linux,pci-domain = <5>;
 
+		pinctrl-names = "default";
+		pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
+
 		clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>,
 			<&bpmp TEGRA194_CLK_PEX1_CORE_5M>;
 		clock-names = "core", "core_m";
-- 
2.17.1