Received: by 2002:a25:8b12:0:0:0:0:0 with SMTP id i18csp4854360ybl; Mon, 26 Aug 2019 17:34:10 -0700 (PDT) X-Google-Smtp-Source: APXvYqwok8mKOyw3Q9bg3WFgkZ9WveAsxNSLVAybIJ8kKpqOSbxX9dcFUafhTUEdpJhrBPLq9644 X-Received: by 2002:a65:4948:: with SMTP id q8mr18674633pgs.214.1566866050429; Mon, 26 Aug 2019 17:34:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1566866050; cv=none; d=google.com; s=arc-20160816; b=dz5zYC4D3LH7Sabv27b2ebeQNOzDGp1Yr3l7KccrNsE+OF8R69Ri4+9KqVnitbGklX SXtTb+JwPh66nDtpidqyrgQAc0pyg5L1pfA8bPuWrTYYWJJDixh3aSkrLb1C5oMuD6vm km60x9LXBHXn0zy3cYx/4ZLO7X0urdxUvVK+hO9a7YDGaVKd+457LU5507fVgjux3vGE 27ACybv5RHH6r9ICveaKRye8lk9FYSxnnvivcKXJ8+PhFGr80Kbikb+0C+9gTp4u66EX LdEWGVD/iEGZTJqvKiJtDg/KjodMPFKdxyXj7qZMrCwvAtiYPj3pBX8Od9LaZUqWJa3l GADw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=189g0JP68z9u+Ep1GWrcVIMocc6+TBCdAX4Yd+2DXKM=; b=MEUrdHqkLcK7Ix2CRKrh1AMyiJVJ5weS6PaAorhvgz6ndwv0PznRWDgygDeZNYqOaW pzna1yyxpW1+GFJFSO4D8YlgFE5kh5syCmSL7cHVambniDFDBNr3b01EcuI0KOk06REW WMnJSLZs8w7gjVqCxX6x5T2ZRQQOo+gaaOjxlJNt/FqyDriwa6Ggf/s20PxbBehcqwGQ EsMzkIg38rpwJaKoOBePOGGHVRpEfGoYZWYicvbaB1p2+KZxGgH/5wYbvYHLYMjWwro6 HEh1RoePLgaLOFyBdjEW18mba/cXbMFxtYAJb2S15JX80lXClpEnaZHJo2W/EXq+IMDz Mxcg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=KuztGt+n; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v21si10996304ply.131.2019.08.26.17.33.55; Mon, 26 Aug 2019 17:34:10 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20161025 header.b=KuztGt+n; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728115AbfH0Acy (ORCPT + 99 others); Mon, 26 Aug 2019 20:32:54 -0400 Received: from mail-pl1-f195.google.com ([209.85.214.195]:36765 "EHLO mail-pl1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726596AbfH0Acy (ORCPT ); Mon, 26 Aug 2019 20:32:54 -0400 Received: by mail-pl1-f195.google.com with SMTP id f19so10858364plr.3; Mon, 26 Aug 2019 17:32:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=189g0JP68z9u+Ep1GWrcVIMocc6+TBCdAX4Yd+2DXKM=; b=KuztGt+nXT1gTEb5csKxCYy4+7BmsyakHzvzGyMtFyRqmTySJrI0NB05w5Fuz9nO48 Llgge4WwGN02rS9wUnnTdnQ/8KTvKkSVAK65Xvz5ruXm9HJ/x1L8jehOEu+pr3Jswa54 zxMllUu66M0CF70bAOEpGjK/3v9U9Jk77jgDAboFs3uCWkTdLWejqzFeJULd0F7pPcr6 UlRxO4l5oBhdnM0UBeXqxOcYZV8N5GzwoAt92jTFDJWGTaer2jdvopGcTkdP7Hsou0gA lkrMHx0BxVijrWQ12Br1pQ1jJdTf+Onhh3C1RgDPJdei85GLeIvbroXUB+2PDB3DPSgq ormQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=189g0JP68z9u+Ep1GWrcVIMocc6+TBCdAX4Yd+2DXKM=; b=n19u1XSsm0hIZVvdPB8vvBY9RqSIdtkDlEI4Oi0nprZ/IZlBzDdAaSYUsjBIDqFbu3 Ho5G+KNW+F4sivtBkEbciW4vtVkTW4rMlUbNdrLl6P8U7BSkb5nU8HSX7DmJMIN7tfT8 2lHDEP/DBGW77KfzhmDG5/T7ZsYpUVrvDG14jl+bcIUP3Z/6XCsyGmyif9S/WH4ys1If kw2IRx52259qE10XGQKxPSL4XWIlX9f5B/0hOoXEeugC/o+GsUVZBU2yAKx6kih/6EHI 3u1QyAd4jZiwfTJeyNOCVe7eLTG/m6Ql4eTHyFP5K09XTeNQCSf2GW40b9AlUD5Mf8mh hIQg== X-Gm-Message-State: APjAAAXO9Z9iPkE44ZdzXObvMLEtKbCp6fP8Vk0YzSgUkkTesAF2S7V/ xZD8aeH9qrEp5pd7yJLpwQs= X-Received: by 2002:a17:902:5c3:: with SMTP id f61mr20153314plf.98.1566865973709; Mon, 26 Aug 2019 17:32:53 -0700 (PDT) Received: from gli-arch.genesyslogic.com.tw (60-251-58-169.HINET-IP.hinet.net. [60.251.58.169]) by smtp.gmail.com with ESMTPSA id l7sm7444220pff.35.2019.08.26.17.32.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Aug 2019 17:32:52 -0700 (PDT) From: Ben Chuang To: adrian.hunter@intel.com, ulf.hansson@linaro.org Cc: linux-mmc@vger.kernel.org, linux-kernel@vger.kernel.org, johnsonm@danlj.org, ben.chuang@genesyslogic.com.tw, Ben Chuang Subject: [PATCH V6 2/5] mmc: sdhci: Add PLL Enable support to internal clock setup Date: Tue, 27 Aug 2019 08:32:55 +0800 Message-Id: <20190827003255.2347-1-benchuanggli@gmail.com> X-Mailer: git-send-email 2.22.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ben Chuang The GL9750 and GL9755 chipsets, and possibly others, require PLL Enable setup as part of the internal clock setup as described in 3.2.1 Internal Clock Setup Sequence of SD Host Controller Simplified Specification Version 4.20. Signed-off-by: Ben Chuang Co-developed-by: Michael K Johnson Signed-off-by: Michael K Johnson Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci.c | 23 +++++++++++++++++++++++ drivers/mmc/host/sdhci.h | 1 + 2 files changed, 24 insertions(+) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index bed0760a6c2a..9106ebc7a422 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1653,6 +1653,29 @@ void sdhci_enable_clk(struct sdhci_host *host, u16 clk) udelay(10); } + if (host->version >= SDHCI_SPEC_410 && host->v4_mode) { + clk |= SDHCI_CLOCK_PLL_EN; + clk &= ~SDHCI_CLOCK_INT_STABLE; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + /* Wait max 150 ms */ + timeout = ktime_add_ms(ktime_get(), 150); + while (1) { + bool timedout = ktime_after(ktime_get(), timeout); + + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + if (clk & SDHCI_CLOCK_INT_STABLE) + break; + if (timedout) { + pr_err("%s: PLL clock never stabilised.\n", + mmc_hostname(host->mmc)); + sdhci_dumpregs(host); + return; + } + udelay(10); + } + } + clk |= SDHCI_CLOCK_CARD_EN; sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); } diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 199712e7adbb..72601a4d2e95 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -114,6 +114,7 @@ #define SDHCI_DIV_HI_MASK 0x300 #define SDHCI_PROG_CLOCK_MODE 0x0020 #define SDHCI_CLOCK_CARD_EN 0x0004 +#define SDHCI_CLOCK_PLL_EN 0x0008 #define SDHCI_CLOCK_INT_STABLE 0x0002 #define SDHCI_CLOCK_INT_EN 0x0001 -- 2.22.1