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From:   Peng Fan <peng.fan@nxp.com>
To:     "mturquette@baylibre.com" <mturquette@baylibre.com>,
        "sboyd@kernel.org" <sboyd@kernel.org>,
        "shawnguo@kernel.org" <shawnguo@kernel.org>,
        "s.hauer@pengutronix.de" <s.hauer@pengutronix.de>,
        "festevam@gmail.com" <festevam@gmail.com>,
        Aisheng Dong <aisheng.dong@nxp.com>
CC:     "kernel@pengutronix.de" <kernel@pengutronix.de>,
        dl-linux-imx <linux-imx@nxp.com>,
        Anson Huang <anson.huang@nxp.com>,
        Jacky Bai <ping.bai@nxp.com>, Abel Vesa <abel.vesa@nxp.com>,
        "linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
        "linux-arm-kernel@lists.infradead.org" 
        <linux-arm-kernel@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Peng Fan <peng.fan@nxp.com>
Subject: [PATCH] clk: imx: lpcg: write twice when writing lpcg regs
Thread-Topic: [PATCH] clk: imx: lpcg: write twice when writing lpcg regs
Thread-Index: AQHVXK/qRNohGClvt0yC94cqOwkPUA==
Date:   Tue, 27 Aug 2019 08:17:50 +0000
Message-ID: <1566936978-28519-1-git-send-email-peng.fan@nxp.com>
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From: Peng Fan <peng.fan@nxp.com>

There is hardware issue that:
The output clock the LPCG cell will not turn back on as expected,
even though a read of the IPG registers in the LPCG indicates that
the clock should be enabled.

The software workaround is to write twice to enable the LPCG clock
output.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
 drivers/clk/imx/clk-lpcg-scu.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/clk/imx/clk-lpcg-scu.c b/drivers/clk/imx/clk-lpcg-scu.=
c
index a73a799fb777..7391d0668ec4 100644
--- a/drivers/clk/imx/clk-lpcg-scu.c
+++ b/drivers/clk/imx/clk-lpcg-scu.c
@@ -54,6 +54,11 @@ static int clk_lpcg_scu_enable(struct clk_hw *hw)
=20
 	reg |=3D val << clk->bit_idx;
 	writel(reg, clk->reg);
+	/*
+	 * There is hardware bug. When enabling the LPCG clock
+	 * output, SW can write the enabling value twice
+	 */
+	writel(reg, clk->reg);
=20
 	spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags);
=20
@@ -71,6 +76,11 @@ static void clk_lpcg_scu_disable(struct clk_hw *hw)
 	reg =3D readl_relaxed(clk->reg);
 	reg &=3D ~(CLK_GATE_SCU_LPCG_MASK << clk->bit_idx);
 	writel(reg, clk->reg);
+	/*
+	 * There is hardware bug. When enabling the LPCG clock
+	 * output, SW can write the enabling value twice
+	 */
+	writel(reg, clk->reg);
=20
 	spin_unlock_irqrestore(&imx_lpcg_scu_lock, flags);
 }
--=20
2.16.4