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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id u5sm4384898oic.45.2019.08.27.08.56.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Aug 2019 08:56:27 -0700 (PDT) Date: Tue, 27 Aug 2019 10:56:26 -0500 From: Rob Herring To: =?iso-8859-1?Q?Andr=E9?= Draszik Cc: linux-kernel@vger.kernel.org, Richard Zhu , Lucas Stach , Bjorn Helgaas , Mark Rutland , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: Re: [PATCH 2/2] dt-bindings: imx6q-pcie: add "fsl,pcie-phy-refclk-internal" for i.MX7D Message-ID: <20190827155626.GA29948@bogus> References: <20190813103759.38358-1-git@andred.net> <20190813103759.38358-2-git@andred.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20190813103759.38358-2-git@andred.net> User-Agent: Mutt/1.10.1 (2018-07-13) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Aug 13, 2019 at 11:37:59AM +0100, Andr? Draszik wrote: > The i.MX7D variant of the IP can use either an external > crystal oscillator input or an internal clock input as > a reference clock input for the PCIe PHY. > > Document the optional property 'fsl,pcie-phy-refclk-internal' > > Signed-off-by: Andr? Draszik > Cc: Richard Zhu > Cc: Lucas Stach > Cc: Bjorn Helgaas > Cc: Rob Herring > Cc: Mark Rutland > Cc: Shawn Guo > Cc: Sascha Hauer > Cc: Pengutronix Kernel Team > Cc: Fabio Estevam > Cc: NXP Linux Team > Cc: linux-pci@vger.kernel.org > Cc: linux-arm-kernel@lists.infradead.org > Cc: devicetree@vger.kernel.org > Cc: linux-kernel@vger.kernel.org > --- > Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt > index a7f5f5afa0e6..985d7083df9f 100644 > --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt > @@ -56,6 +56,11 @@ Additional required properties for imx7d-pcie and imx8mq-pcie: > - "turnoff" > - fsl,imx7d-pcie-phy: A phandle to an fsl,imx7d-pcie-phy node. Not sure how this got in, but why is the phy binding not used here? > > +Additional optional properties for imx7d-pcie: > +- fsl,pcie-phy-refclk-internal: If present then an internal PLL input is used > + as PCIe PHY reference clock source. By default an external ocsillator input > + is used. Can't the clock binding and maybe 'assigned-clocks' be used here? Also, this is a property of the PHY, so it belongs in the PHY's node. Rob