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[209.132.180.67]) by mx.google.com with ESMTP id o131si1952338pgo.445.2019.08.28.04.42.09; Wed, 28 Aug 2019 04:42:25 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=default header.b="Z3/ECLQS"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726429AbfH1Ljq (ORCPT + 99 others); Wed, 28 Aug 2019 07:39:46 -0400 Received: from mail.kernel.org ([198.145.29.99]:44610 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726326AbfH1Ljp (ORCPT ); Wed, 28 Aug 2019 07:39:45 -0400 Received: from mail-qk1-f175.google.com (mail-qk1-f175.google.com [209.85.222.175]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 77A5522CF8; Wed, 28 Aug 2019 11:39:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1566992384; bh=zFX6K+sbahwAVHjk1v7Y0ynjPUeiaUDUZEEnuIPaDo8=; h=References:In-Reply-To:From:Date:Subject:To:Cc:From; b=Z3/ECLQSL7wh6MTn4A6x8vrX9g0jEHKxPtPHd5PCTw3kwe/Fp9kW1Ac3KXrvyj9dd Tx3djCmBNmPpfRxvVo3+UzcdKLw85GTS1mFE41y7DB6G0mcvo/QGr0BBkl+ixXzzr5 EnGmjCSAGTArW7nvFbEafw1P4Lu+wdh8o4SvAJzQ= Received: by mail-qk1-f175.google.com with SMTP id w18so2093902qki.0; Wed, 28 Aug 2019 04:39:44 -0700 (PDT) X-Gm-Message-State: APjAAAUozvkvtKAUd+Elz/fHMVMBdztl3NPW3YADG1QQcRb2Gdbei1f9 NchL/PSxc/aA2xrWYaga6bNFB2Rk0bHv4xTzcQ== X-Received: by 2002:a37:d8f:: with SMTP id 137mr3443285qkn.254.1566992383614; Wed, 28 Aug 2019 04:39:43 -0700 (PDT) MIME-Version: 1.0 References: <20190827082652.43840-1-vadivel.muruganx.ramuthevar@linux.intel.com> <20190827082652.43840-2-vadivel.muruganx.ramuthevar@linux.intel.com> <2a915595-be5f-83f4-34e8-34d667875cc2@linux.intel.com> In-Reply-To: <2a915595-be5f-83f4-34e8-34d667875cc2@linux.intel.com> From: Rob Herring Date: Wed, 28 Aug 2019 06:39:32 -0500 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v1 1/2] dt-bindings: phy: intel-sdxc-phy: Add YAML schema for LGM SDXC PHY To: "Ramuthevar, Vadivel MuruganX" Cc: Kishon Vijay Abraham I , "linux-kernel@vger.kernel.org" , devicetree@vger.kernel.org, Andy Shevchenko , cheol.yong.kim@intel.com, qi-ming.wu@intel.com, peter.harliman.liem@intel.com Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Aug 27, 2019 at 10:47 PM Ramuthevar, Vadivel MuruganX wrote: > > Hi Rob, > > On 27/8/2019 8:39 PM, Rob Herring wrote: > > On Tue, Aug 27, 2019 at 3:27 AM Ramuthevar,Vadivel MuruganX > > wrote: > >> From: Ramuthevar Vadivel Murugan > >> > >> Add a YAML schema to use the host controller driver with the > >> SDXC PHY on Intel's Lightning Mountain SoC. > >> > >> Signed-off-by: Ramuthevar Vadivel Murugan > >> --- > >> .../bindings/phy/intel,lgm-sdxc-phy.yaml | 50 ++++++++++++++++++++++ > >> 1 file changed, 50 insertions(+) > >> create mode 100644 Documentation/devicetree/bindings/phy/intel,lgm-sdxc-phy.yaml > >> > >> diff --git a/Documentation/devicetree/bindings/phy/intel,lgm-sdxc-phy.yaml b/Documentation/devicetree/bindings/phy/intel,lgm-sdxc-phy.yaml > >> new file mode 100644 > >> index 000000000000..be05020880bf > >> --- /dev/null > >> +++ b/Documentation/devicetree/bindings/phy/intel,lgm-sdxc-phy.yaml > >> @@ -0,0 +1,50 @@ > >> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > >> +%YAML 1.2 > >> +--- > >> +$id: http://devicetree.org/schemas/phy/intel,lgm-sdxc-phy.yaml# > >> +$schema: http://devicetree.org/meta-schemas/core.yaml# > >> + > >> +title: Intel Lightning Mountain(LGM) SDXC PHY Device Tree Bindings > >> + > >> +maintainers: > >> + - Ramuthevar Vadivel Murugan > >> + > >> +description: Binding for SDXC PHY > >> + > >> +properties: > >> + compatible: > >> + const: intel,lgm-sdxc-phy > >> + > >> + intel,syscon: > >> + description: phandle to the sdxc through syscon > >> + $ref: '/schemas/types.yaml#/definitions/phandle' > >> + > >> + clocks: > >> + maxItems: 1 > >> + > >> + clock-names: > >> + maxItems: 1 > >> + > >> + "#phy-cells": > >> + const: 0 > >> + > >> +required: > >> + - "#phy-cells" > >> + - compatible > >> + - intel,syscon > >> + - clocks > >> + - clock-names > >> + > >> +additionalProperties: false > >> + > >> +examples: > >> + - | > >> + sdxc_phy: sdxc_phy { > >> + compatible = "intel,lgm-sdxc-phy"; > >> + intel,syscon = <&sysconf>; > > Rather than a phandle, can this be a child node of sysconf? You need a > > binding for sysconf first anyways. > intel,syscon is phandle, emmc_phy is not child node of sysconf, access > emmc_phy > register over sysconf so made as reference here. How do you access the emmc_phy registers? They are part of the sysconf address space or the sysconf provides some sort of indirect register access? In case of the former, then emmc_phy should be a child node. That's actually fairly common. Rob