Received: by 2002:a25:8b12:0:0:0:0:0 with SMTP id i18csp2956753ybl;
        Thu, 29 Aug 2019 15:46:53 -0700 (PDT)
X-Google-Smtp-Source: APXvYqylMgpl64flKF+RUVWYvlErAr6RxiHY8ZNhadmmUVMk7zUwHFIRuchSy9mqEOLTrDcRrIh+
X-Received: by 2002:a63:6888:: with SMTP id d130mr9970255pgc.197.1567118813051;
        Thu, 29 Aug 2019 15:46:53 -0700 (PDT)
ARC-Seal: i=1; a=rsa-sha256; t=1567118813; cv=none;
        d=google.com; s=arc-20160816;
        b=n6HuDTKv6VkqcRvvCZ4hA2CagaQpOSpdH6miPTHV5LqHUvYsCl3PqBg0HNS9QDYAfU
         FSJiBEjKubZg3JxPOTYsCA1k1c2twgqXqS1re5d+GsLs0YjNXsakJaTWDXKF/82QRSQA
         0UsGp99VEZWSLaLSmcEf9GR6EYWdb9W1TgHjzgqwtZnb9/n9kN52l/E0DstNj3HKPCcb
         fja8+xuWic7EbzFm8sPu0GjssLp9o4QnoRjTjKdaSLhGmCYpIxcbPCEwDVTh8SnCh3bW
         Rft6awUsRrmury03wwmFYrjHId6KryuqqF3K/bcrX/FVxPd9kvnEei2Mepj6mIe+8WN7
         ggow==
ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816;
        h=list-id:precedence:sender:to:dkim-signature:mime-version:references
         :in-reply-to:message-id:date:subject:cc:from;
        bh=eBq8+pmSZ4GEOeaq+B+bPoC14S2kYmqdfA9PyT31IhY=;
        b=SynYhdmsNVzdUl6dAQDXh3YRmh5pLqW1BECR2/BJ2TupUnJA3FP7l+LiUWyJU86Ep+
         1Z30SSPjNLO+G7DyW2f1/L2wgU1hoqPoLFB+9R9ArzxFt7gUufNhZGBOOYMavHbQkd1y
         +lBzdLxFcngBAIt2qnOmQnQtGo3Xz+4u7P3mR9elXnjLWczByQiQbUOO+RpxiKS2X372
         +s73QHmwWAdLd4Wyd6H/3Jaf9VI1rNtULoJv9a974GNB3VodeCImzsh+8nbVhKZv9VzC
         JAt3k89w2bjPWthChauRuAwGtyUQCuwRCqU+VZ4vDzjooyrAiPK+vUuqCcFVaIT8fXaf
         ib5w==
ARC-Authentication-Results: i=1; mx.google.com;
       dkim=fail header.i=@nvidia.com header.s=n1 header.b=ChPGfFaD;
       spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
       dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com
Return-Path: <linux-kernel-owner@vger.kernel.org>
Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67])
        by mx.google.com with ESMTP id 28si3024090pgk.331.2019.08.29.15.46.37;
        Thu, 29 Aug 2019 15:46:53 -0700 (PDT)
Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
Authentication-Results: mx.google.com;
       dkim=fail header.i=@nvidia.com header.s=n1 header.b=ChPGfFaD;
       spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org;
       dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nvidia.com
Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand
        id S1728407AbfH2Wpo (ORCPT <rfc822;zffurovfq63@gmail.com>
        + 99 others); Thu, 29 Aug 2019 18:45:44 -0400
Received: from hqemgate14.nvidia.com ([216.228.121.143]:17663 "EHLO
        hqemgate14.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org
        with ESMTP id S1728262AbfH2Wpn (ORCPT
        <rfc822;linux-kernel@vger.kernel.org>);
        Thu, 29 Aug 2019 18:45:43 -0400
Received: from hqpgpgate102.nvidia.com (Not Verified[216.228.121.13]) by hqemgate14.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA)
        id <B5d6855970001>; Thu, 29 Aug 2019 15:45:43 -0700
Received: from hqmail.nvidia.com ([172.20.161.6])
  by hqpgpgate102.nvidia.com (PGP Universal service);
  Thu, 29 Aug 2019 15:45:43 -0700
X-PGP-Universal: processed;
        by hqpgpgate102.nvidia.com on Thu, 29 Aug 2019 15:45:43 -0700
Received: from HQMAIL107.nvidia.com (172.20.187.13) by HQMAIL105.nvidia.com
 (172.20.187.12) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Thu, 29 Aug
 2019 22:45:42 +0000
Received: from hqnvemgw02.nvidia.com (172.16.227.111) by HQMAIL107.nvidia.com
 (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend
 Transport; Thu, 29 Aug 2019 22:45:42 +0000
Received: from vdumpa-ubuntu.nvidia.com (Not Verified[172.17.173.140]) by hqnvemgw02.nvidia.com with Trustwave SEG (v7,5,8,10121)
        id <B5d6855960006>; Thu, 29 Aug 2019 15:45:42 -0700
From:   Krishna Reddy <vdumpa@nvidia.com>
CC:     <linux-arm-kernel@lists.infradead.org>,
        <iommu@lists.linux-foundation.org>, <linux-kernel@vger.kernel.org>,
        <linux-tegra@vger.kernel.org>, <treding@nvidia.com>,
        <yhsu@nvidia.com>, <snikam@nvidia.com>, <praithatha@nvidia.com>,
        <talho@nvidia.com>, <avanbrunt@nvidia.com>, <thomasz@nvidia.com>,
        <olof@lixom.net>, <jtukkinen@nvidia.com>, <mperttunen@nvidia.com>,
        Krishna Reddy <vdumpa@nvidia.com>
Subject: [PATCH 5/7] arm64: tegra: Add Memory controller DT node on T194
Date:   Thu, 29 Aug 2019 15:47:05 -0700
Message-ID: <1567118827-26358-6-git-send-email-vdumpa@nvidia.com>
X-Mailer: git-send-email 2.1.4
In-Reply-To: <1567118827-26358-1-git-send-email-vdumpa@nvidia.com>
References: <1567118827-26358-1-git-send-email-vdumpa@nvidia.com>
X-NVConfidentiality: public
MIME-Version: 1.0
Content-Type: text/plain
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1;
        t=1567118743; bh=eBq8+pmSZ4GEOeaq+B+bPoC14S2kYmqdfA9PyT31IhY=;
        h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer:
         In-Reply-To:References:X-NVConfidentiality:MIME-Version:
         Content-Type;
        b=ChPGfFaDq2kV5w2ayQQp9zljYQ5CcUlIYDR+iUDDoU72wHFTKpYJwD4ojEzKEiGfG
         Zu3qdafuGFdosA6xh6PO+nWaU4uBXcOtO/KzJGNkdaEDoUr3bFevEXiOIarEZl4R0w
         VCKmsbSPJr8jEdDcnLqd9tsQtEPwn78nTedzPekDYhcrGc83TO32MfSDoqdXhNfcef
         SW3QnC2NYZHLFt1xAVENOQlbKrTjHfmPyf2n41wGUzGsJZgHfYKgQCr7m0Ulfcgbjo
         Gr8isIZC2Dct1ZhYS4/UfwDdpHrEWhgepsJCgXuq671/tsTpxzOCHi4m5jPwjiycGU
         a4GMYV3i4vbIw==
To:     unlisted-recipients:; (no To-header on input)
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

Add Memory controller DT node on T194 and enable it.
This patch is a prerequisite for SMMU enable on T194.

Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi | 4 ++++
 arch/arm64/boot/dts/nvidia/tegra194.dtsi       | 7 +++++++
 2 files changed, 11 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
index 62e07e11..4b3441b 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194-p2888.dtsi
@@ -47,6 +47,10 @@
 			};
 		};
 
+		memory-controller@2c00000 {
+			status = "okay";
+		};
+
 		serial@3110000 {
 			status = "okay";
 		};
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index adebbbf..d906958 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -6,6 +6,7 @@
 #include <dt-bindings/reset/tegra194-reset.h>
 #include <dt-bindings/power/tegra194-powergate.h>
 #include <dt-bindings/thermal/tegra194-bpmp-thermal.h>
+#include <dt-bindings/memory/tegra186-mc.h>
 
 / {
 	compatible = "nvidia,tegra194";
@@ -130,6 +131,12 @@
 			};
 		};
 
+		memory-controller@2c00000 {
+			compatible = "nvidia,tegra186-mc";
+			reg = <0x02c00000 0xb0000>;
+			status = "disabled";
+		};
+
 		uarta: serial@3100000 {
 			compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
 			reg = <0x03100000 0x40>;
-- 
2.1.4