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To:     Paul Walmsley <paul.walmsley@sifive.com>
Cc:     linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
        Palmer Dabbelt <palmer@sifive.com>,
        Rob Herring <robh@kernel.org>,
        Albert Ou <aou@eecs.berkeley.edu>,
        Andrew Waterman <andrew@sifive.com>,
        Mike Rapoport <rppt@linux.ibm.com>,
        Zong Li <zong@andestech.com>,
        Michael Clark <michaeljclark@mac.com>,
        Olof Johansson <olof@lixom.net>,
        Greentime Hu <greentime.hu@sifive.com>,
        Stephen Bates <sbates@raithlin.com>,
        Christoph Hellwig <hch@lst.de>
References: <20190828214054.3562-1-logang@deltatee.com>
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From:   Logan Gunthorpe <logang@deltatee.com>
Message-ID: <58b828bd-d691-f460-49aa-7e6f15180343@deltatee.com>
Date:   Thu, 29 Aug 2019 17:41:52 -0600
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Subject: Re: [PATCH v6] RISC-V: Implement sparsemem
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On 2019-08-29 5:38 p.m., Paul Walmsley wrote:
>> +#ifdef CONFIG_SPARSEMEM
>> +#define MAX_PHYSMEM_BITS	CONFIG_PA_BITS
>> +#define SECTION_SIZE_BITS	27
> 
> Do you have a specific rationale behind this selection, or is this simply 
> a reasonable starting point?

It's inline with what other platforms are doing. So in some ways it's a
reasonable starting point but I don't see any reason to change it in the
near term.

>> +#endif /* CONFIG_SPARSEMEM */
>> +
>> +#endif /* __ASM_SPARSEMEM_H */
> 
> The following is what I'm getting ready to queue.

Great, thanks!

Logan