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From:   Jethro Beekman <jethro@fortanix.com>
To:     Mika Westerberg <mika.westerberg@linux.intel.com>
CC:     Marek Vasut <marek.vasut@gmail.com>,
        Tudor Ambarus <tudor.ambarus@microchip.com>,
        David Woodhouse <dwmw2@infradead.org>,
        Brian Norris <computersforpeace@gmail.com>,
        Miquel Raynal <miquel.raynal@bootlin.com>,
        Richard Weinberger <richard@nod.at>,
        Vignesh Raghavendra <vigneshr@ti.com>,
        Allison Randal <allison@lohutok.net>,
        Thomas Gleixner <tglx@linutronix.de>,
        Enrico Weigelt <info@metux.net>,
        "linux-mtd@lists.infradead.org" <linux-mtd@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 2/2] mtd: spi-nor: intel-spi: add support for Intel Cannon
 Lake SPI flash
Thread-Topic: [PATCH 2/2] mtd: spi-nor: intel-spi: add support for Intel
 Cannon Lake SPI flash
Thread-Index: AQHVX8ABRdU28yqEZUSYr3dEEhcW0acVQqAAgAAfk4A=
Date:   Sat, 31 Aug 2019 15:29:21 +0000
Message-ID: <74545c4c-a9fc-77c8-cb54-6fbf747f0eea@fortanix.com>
References: <6cc18e41-82a6-942b-6d91-6297f73a33da@fortanix.com>
 <20190831133616.GQ3177@lahna.fi.intel.com>
In-Reply-To: <20190831133616.GQ3177@lahna.fi.intel.com>
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On 2019-08-31 06:36, Mika Westerberg wrote:
> Looks like some white space damage. There are couple of similar below a=
s
> well.

Oops. I will fix this in a v2 or resend later.

>> +		ispi->sregs =3D NULL;
>> +		ispi->pregs =3D ispi->base + CNL_PR;
>> +		ispi->nregions =3D CNL_FREG_NUM;
>> +		ispi->pr_num =3D CNL_PR_NUM;
>=20
> Does CNL really have a different number of PR and FR regions than the
> previous generations?

I'm using this as a reference:=20
https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/3=
00-series-chipset-pch-datasheet-vol-2.pdf=20
=2E If you have more accurate information, please let me know.

--
Jethro Beekman | Fortanix


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