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[209.132.180.67]) by mx.google.com with ESMTP id t18si11590519pjr.102.2019.09.02.03.43.48; Mon, 02 Sep 2019 03:44:03 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730900AbfIBKlM (ORCPT + 99 others); Mon, 2 Sep 2019 06:41:12 -0400 Received: from foss.arm.com ([217.140.110.172]:51862 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730233AbfIBKlL (ORCPT ); Mon, 2 Sep 2019 06:41:11 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 123DC28; Mon, 2 Sep 2019 03:41:11 -0700 (PDT) Received: from localhost (unknown [10.37.6.20]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 563FF3F246; Mon, 2 Sep 2019 03:41:10 -0700 (PDT) Date: Mon, 2 Sep 2019 11:41:08 +0100 From: Andrew Murray To: Vidya Sagar Cc: lorenzo.pieralisi@arm.com, bhelgaas@google.com, robh+dt@kernel.org, thierry.reding@gmail.com, jonathanh@nvidia.com, kishon@ti.com, gustavo.pimentel@synopsys.com, digetx@gmail.com, mperttunen@nvidia.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kthota@nvidia.com, mmaddireddy@nvidia.com, sagar.tv@gmail.com Subject: Re: [PATCH V3 2/6] dt-bindings: PCI: tegra: Add PCIe slot supplies regulator entries Message-ID: <20190902104108.GC9720@e119886-lin.cambridge.arm.com> References: <20190828172850.19871-1-vidyas@nvidia.com> <20190828172850.19871-3-vidyas@nvidia.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20190828172850.19871-3-vidyas@nvidia.com> User-Agent: Mutt/1.10.1+81 (426a6c1) (2018-08-26) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, Aug 28, 2019 at 10:58:46PM +0530, Vidya Sagar wrote: > Add optional bindings "vpcie3v3-supply" and "vpcie12v-supply" to describe > regulators of a PCIe slot's supplies 3.3V and 12V provided the platform > is designed to have regulator controlled slot supplies. > > Signed-off-by: Vidya Sagar Reviewed-by: Andrew Murray > --- > V3: > * None > > V2: > * None > > .../devicetree/bindings/pci/nvidia,tegra194-pcie.txt | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt > index 0ac1b867ac24..b739f92da58e 100644 > --- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt > +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt > @@ -104,6 +104,12 @@ Optional properties: > specified in microseconds > - nvidia,aspm-l0s-entrance-latency-us: ASPM L0s entrance latency to be > specified in microseconds > +- vpcie3v3-supply: A phandle to the regulator node that supplies 3.3V to the slot > + if the platform has one such slot. (Ex:- x16 slot owned by C5 controller > + in p2972-0000 platform). > +- vpcie12v-supply: A phandle to the regulator node that supplies 12V to the slot > + if the platform has one such slot. (Ex:- x16 slot owned by C5 controller > + in p2972-0000 platform). > > Examples: > ========= > @@ -156,6 +162,8 @@ Tegra194: > 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory (16GB) */ > > vddio-pex-ctl-supply = <&vdd_1v8ao>; > + vpcie3v3-supply = <&vdd_3v3_pcie>; > + vpcie12v-supply = <&vdd_12v_pcie>; > > phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>, > <&p2u_hsio_5>; > -- > 2.17.1 >