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[163.172.81.188]) by smtp.googlemail.com with ESMTPSA id f15sm7507365wml.8.2019.09.02.09.03.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Sep 2019 09:03:49 -0700 (PDT) From: Jerome Brunet To: Kevin Hilman Cc: Jerome Brunet , linux-amlogic@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH] arm64: dts: meson: sm1: set gpio interrupt controller compatible Date: Mon, 2 Sep 2019 18:03:34 +0200 Message-Id: <20190902160334.14321-1-jbrunet@baylibre.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-Patchwork-Bot: notify Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Set the appropriate gpio interrupt controller compatible for the sm1 SoC family. This newer version of the controller can now trig irq on both edge of the input signal Signed-off-by: Jerome Brunet --- arch/arm64/boot/dts/amlogic/meson-sm1.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi index 521573f3a5ba..6152e928aef2 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi @@ -134,6 +134,11 @@ power-domains = <&pwrc PWRC_SM1_ETH_ID>; }; +&gpio_intc { + compatible = "amlogic,meson-sm1-gpio-intc", + "amlogic,meson-gpio-intc"; +}; + &pwrc { compatible = "amlogic,meson-sm1-pwrc"; }; -- 2.21.0