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From:   Paul Burton <paul.burton@mips.com>
To:     Rob Herring <robh+dt@kernel.org>,
        Jiaxun Yang <jiaxun.yang@flygoat.com>
CC:     "open list:MIPS" <linux-mips@vger.kernel.org>,
        Huacai Chen <chenhc@lemote.com>,
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        Marc Zyngier <maz@kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Mark Rutland <mark.rutland@arm.co>,
        "devicetree@vger.kernel.org" <devicetree@vger.kernel.org>
Subject: Re: [PATCH 11/13] dt-bindings: mips: Add loongson cpus & boards
Thread-Topic: [PATCH 11/13] dt-bindings: mips: Add loongson cpus & boards
Thread-Index: AQHVYjcQZOaz4gEz0kSE1jLx3WD3zQ==
Date:   Tue, 3 Sep 2019 09:07:51 +0000
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Hi Rob,

On Mon, Sep 02, 2019 at 03:50:47PM +0100, Rob Herring wrote:
> > In general on MIPS we detect CPU properties at runtime from coprocessor
> > 0 registers & similar sources of information, so there's not really a
> > need to specify anything about the CPU in devicetree.
>=20
> We thought the same thing initially for Arm... Mostly what is in DT is
> not what is discoverable. Are clock speeds, power domains, low power
> states, etc. all discoverable?

No, that's a good point - clocks etc may need to be specified in DT. I
just don't see any of that in this patchset - it appears all that is
specified is cache sizes which we already detect. So in this case I
don't see a need for including CPUs in DT at all.

Jiaxun - did you add all this information to DT to avoid the "cacheinfo:
Unable to detect cache hierarchy for CPU" messages during boot? If so
that should be fixed by commit b8bea8a5e5d9 ("mips: fix cacheinfo"). If
not, could you describe why the CPU nodes are needed here?

Thanks,
    Paul