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In-Reply-To: <20190903085823.s4amn27pewc54hl2@kamzik.brq.redhat.com>
From:   Anup Patel <anup@brainfault.org>
Date:   Tue, 3 Sep 2019 14:56:29 +0530
Message-ID: <CAAhSdy1p3KG-m_Gw4LzeY+ap3reVpx+FNjugnDJEDj_-jhgc2w@mail.gmail.com>
Subject: Re: [PATCH v6 10/21] RISC-V: KVM: Handle MMIO exits for VCPU
To:     Andrew Jones <drjones@redhat.com>
Cc:     Anup Patel <Anup.Patel@wdc.com>,
        Palmer Dabbelt <palmer@sifive.com>,
        Paul Walmsley <paul.walmsley@sifive.com>,
        Paolo Bonzini <pbonzini@redhat.com>,
        Radim K <rkrcmar@redhat.com>,
        Daniel Lezcano <daniel.lezcano@linaro.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Atish Patra <Atish.Patra@wdc.com>,
        Alistair Francis <Alistair.Francis@wdc.com>,
        Damien Le Moal <Damien.LeMoal@wdc.com>,
        Christoph Hellwig <hch@infradead.org>,
        "kvm@vger.kernel.org" <kvm@vger.kernel.org>,
        "linux-riscv@lists.infradead.org" <linux-riscv@lists.infradead.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
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On Tue, Sep 3, 2019 at 2:28 PM Andrew Jones <drjones@redhat.com> wrote:
>
> On Thu, Aug 29, 2019 at 01:56:18PM +0000, Anup Patel wrote:
> >  int kvm_riscv_vcpu_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run)
> >  {
> > -     /* TODO: */
> > +     u8 data8;
> > +     u16 data16;
> > +     u32 data32;
> > +     u64 data64;
> > +     ulong insn;
> > +     int len, shift;
> > +
> > +     insn = vcpu->arch.mmio_decode.insn;
> > +
> > +     if (run->mmio.is_write)
> > +             goto done;
> > +
> > +     len = vcpu->arch.mmio_decode.len;
> > +     shift = vcpu->arch.mmio_decode.shift;
> > +
> > +     switch (len) {
> > +     case 1:
> > +             data8 = *((u8 *)run->mmio.data);
> > +             SET_RD(insn, &vcpu->arch.guest_context,
> > +                     (ulong)data8 << shift >> shift);
> > +             break;
> > +     case 2:
> > +             data16 = *((u16 *)run->mmio.data);
> > +             SET_RD(insn, &vcpu->arch.guest_context,
> > +                     (ulong)data16 << shift >> shift);
> > +             break;
> > +     case 4:
> > +             data32 = *((u32 *)run->mmio.data);
> > +             SET_RD(insn, &vcpu->arch.guest_context,
> > +                     (ulong)data32 << shift >> shift);
> > +             break;
> > +     case 8:
> > +             data64 = *((u64 *)run->mmio.data);
> > +             SET_RD(insn, &vcpu->arch.guest_context,
> > +                     (ulong)data64 << shift >> shift);
> > +             break;
> > +     default:
> > +             return -ENOTSUPP;
> > +     };
> > +
> > +done:
> > +     /* Move to next instruction */
> > +     vcpu->arch.guest_context.sepc += INSN_LEN(insn);
> > +
>
> As I pointed out in the last review, just moving this instruction skip
> here is not enough. Doing so introduces the same problem that 2113c5f62b74
> ("KVM: arm/arm64: Only skip MMIO insn once") fixes for arm.

Thanks Drew, I had seen your comment previously but forgot
to address it in v6. I will address it in v7.

Regards,
Anup