Received: by 2002:a25:c593:0:0:0:0:0 with SMTP id v141csp1774905ybe; Tue, 3 Sep 2019 03:20:42 -0700 (PDT) X-Google-Smtp-Source: APXvYqzzQOAnuW5sfT/i+ckpphzNramDhIRKB8aU86Lj7D+MRKoEHyS/1ETTdLa05OnSXt1cKmqB X-Received: by 2002:aa7:908b:: with SMTP id i11mr37501918pfa.199.1567506042428; Tue, 03 Sep 2019 03:20:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1567506042; cv=none; d=google.com; s=arc-20160816; b=sVnp6Vh9t8NjFLVpFU9XHvV6kWDFyjnl5vSKLgdYkAM67qjRZmVeQc/Iufq/ETQ4te rMge08DTZVpRR5xmHqx+EKMKu4pYRGeLGYM/cqJkPdC+Gp4gIomEqS8T2Xd4zYOi1SOI JOHv1PeiQSwfRrnD69tPVyT5gvJg0Ab064c5TdoCDhf9uORqJf+/NPvr0PgKPCChIZmw gsY14V2GcF3phv6odyEZ71BPkPQBM1dPxmOludYMu2Mc3CAzhs/cGaElxFrVSV2lHDwS xzfxOqU5sz26+k16yHseOqMbn1MfS72FgYT/jmPx5q1TL0R1aRl20Odh1t6Xwj0KARUr DU2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding :content-language:in-reply-to:mime-version:user-agent:date :message-id:references:cc:to:from:subject:dkim-signature; bh=nRTqcKo/WxW5TqzAmvGzBhBJLV092AmqWAXRSgLL4HQ=; b=RY3kJwxzeXYHW6BFxOcgqFpsSf8M6G9HrjXk6B1Nx/a6YzQo9N47b9L1GytUWVHZLF VVaIFFcNHl99KJ95RnPOFdyfyqDp0akHZPg8W781HAuH+U2sDI5Ze1j1Rs6bbRUpSGr5 5NnHYbsPTCSX17BjR3LYayc4G3BHUqrI0owLUIJVtZxeauls7K+c0dLY0y+fyxZXH8IF 5u4KTnSp35/HMdNSMJ9t4sJveZpRL8Q74C7cYJvV50U75yE4wpD680v1GhEDKr28FQpb c0ghl2JtsFPXY+Rxe4s4uVxUger/TLrK5FJl81yj4rMO9GzS9VQB820Siza/midhSJVS 1bRA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=MAVqHP5r; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v23si14263587pgn.557.2019.09.03.03.20.26; Tue, 03 Sep 2019 03:20:42 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=MAVqHP5r; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728691AbfICKT2 (ORCPT + 99 others); Tue, 3 Sep 2019 06:19:28 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:42974 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727005AbfICKT2 (ORCPT ); Tue, 3 Sep 2019 06:19:28 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x83AJJrI043302; Tue, 3 Sep 2019 05:19:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1567505959; bh=nRTqcKo/WxW5TqzAmvGzBhBJLV092AmqWAXRSgLL4HQ=; h=Subject:From:To:CC:References:Date:In-Reply-To; b=MAVqHP5rCVzAK7qY2G2VaRwl+Eht1wf++tyKAUBDMpBXY1dqWnkSOasWdWuL3UJH0 U1dTBLkeDz1xPdv8fjND7octTCvsoznIQlEEKIsiKu28tOdcGOTTPx52xwX7H2+Mlc 7C8KTXqRqmsSup83zDK3uH75JreICd8llooyx7us= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x83AJJXP081861 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 3 Sep 2019 05:19:19 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 3 Sep 2019 05:19:19 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 3 Sep 2019 05:19:19 -0500 Received: from [192.168.2.6] (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id x83AJHVI102032; Tue, 3 Sep 2019 05:19:17 -0500 Subject: Re: [PATCH 4/5] dt-bindings: dma: ti-edma: Add option for reserved channel ranges From: Peter Ujfalusi To: Rob Herring CC: , , , , , , References: <20190823125618.8133-1-peter.ujfalusi@ti.com> <20190823125618.8133-5-peter.ujfalusi@ti.com> <20190829224728.GA1198@bogus> Message-ID: <15d5dc03-d6ca-f438-f37a-e71298abda95@ti.com> Date: Tue, 3 Sep 2019 13:19:45 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 8bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Rob, On 30/08/2019 8.37, Peter Ujfalusi wrote: > Rob, > > On 30/08/2019 1.47, Rob Herring wrote: >> On Fri, Aug 23, 2019 at 03:56:17PM +0300, Peter Ujfalusi wrote: >>> Similarly to paRAM slots, channels can be used by other cores. >>> >>> Add optional property to configure the reserved channel ranges. >>> >>> Signed-off-by: Peter Ujfalusi >>> --- >>> Documentation/devicetree/bindings/dma/ti-edma.txt | 5 +++++ >>> 1 file changed, 5 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/dma/ti-edma.txt b/Documentation/devicetree/bindings/dma/ti-edma.txt >>> index 4bbc94d829c8..1198682ada99 100644 >>> --- a/Documentation/devicetree/bindings/dma/ti-edma.txt >>> +++ b/Documentation/devicetree/bindings/dma/ti-edma.txt >>> @@ -42,6 +42,9 @@ Optional properties: >>> - ti,edma-reserved-slot-ranges: PaRAM slot ranges which should not be used by >>> the driver, they are allocated to be used by for example the >>> DSP. See example. >>> +- ti,edma-reserved-chan-ranges: channel ranges which should not be used by >>> + the driver, they are allocated to be used by for example the >>> + DSP. See example. >> >> Based on the other thread, I think extending dma-channel-mask to a >> uint32-array makes sense here. > > Yes, that is the reason I have asked on that and I'm in progress of > converting the edma driver to use the dma-channel-mask. > Just need to do some shuffling in the driver to get the mask in a form > usable by the driver. > > I'll send an updated series early next week. How should the dma-channel-mask uint31-array should be documented and used? Basically some EDMA have 32, some 64 channels. This is fine. Let's say I want to mask out channel 0-4 and 24-27 This would look like in case of EDMA with 32 channels: &edma { /* channel 0-4 and 24-27 is not to be used */ dma-channel-mask = <0xf0fffff0>; }; How this should look like in case when I have 64 channels? &edma { /* channel 0-4 and 24-27 is not to be used */ dma-channel-mask = <0xf0fffff0>, <0xffffffff>; }; When I read the u32s then chan_mask[0] is for channel 0-31 (LSB is channel 0) chan_maks[1] is for channel 32-63 (LSB is channel 32) Or: &edma { /* channel 0-4 and 24-27 is not to be used */ dma-channel-mask = <0xffffffff>, <0xf0fffff0>; }; chan_maks[0] is for channel 32-63 (LSB is channel 32) chan_mask[1] is for channel 0-31 (LSB is channel 0) Do you have pointer on already established notion on how to document and handle this? - Péter Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki