Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67;
From:   Nadav Amit <namit@vmware.com>
To:     Dave Hansen <dave.hansen@intel.com>
CC:     Andy Lutomirski <luto@kernel.org>,
        Dave Hansen <dave.hansen@linux.intel.com>,
        "x86@kernel.org" <x86@kernel.org>,
        "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
        Peter Zijlstra <peterz@infradead.org>,
        Thomas Gleixner <tglx@linutronix.de>,
        Ingo Molnar <mingo@redhat.com>
Subject: Re: [RFC PATCH v2 0/3] x86/mm/tlb: Defer TLB flushes with PTI
Thread-Topic: [RFC PATCH v2 0/3] x86/mm/tlb: Defer TLB flushes with PTI
Thread-Index: AQHVWkMKQEoGoFlX+E2oGohYzHeU4KcaIOEAgAAPowA=
Date:   Tue, 3 Sep 2019 16:13:28 +0000
Message-ID: <75004C21-C00A-4C62-9A06-EAB4C7FE7480@vmware.com>
References: <20190823225248.15597-1-namit@vmware.com>
 <f63027ae-2e3a-fac0-69f8-bb11c1b680b0@intel.com>
In-Reply-To: <f63027ae-2e3a-fac0-69f8-bb11c1b680b0@intel.com>
Accept-Language: en-US
Content-Language: en-US
received-spf: None (protection.outlook.com: vmware.com does not designate
 permitted sender hosts)
Content-Type: text/plain; charset="us-ascii"
Content-ID: <DDB7E699C036CC449ED693030515BDE6@namprd05.prod.outlook.com>
Content-Transfer-Encoding: quoted-printable
MIME-Version: 1.0
X-MS-Exchange-CrossTenant-Network-Message-Id: 5d7963d7-4a6f-45e8-04dd-08d73089a842
X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Sep 2019 16:13:28.6446
 (UTC)
X-MS-Exchange-CrossTenant-fromentityheader: Hosted
X-MS-Exchange-CrossTenant-id: b39138ca-3cee-4b4a-a4d6-cd83d9dd62f0
X-MS-Exchange-CrossTenant-mailboxtype: HOSTED
X-MS-Exchange-CrossTenant-userprincipalname: csM7Ja4NoBvqWWqr5RxtfaZmrzV+cLROcB4WT9egw/8tqRG5O09qJwWZx0PaH57taCKxOtU2NfgPHcZs0omysw==
X-MS-Exchange-Transport-CrossTenantHeadersStamped: BYAPR05MB6006
Sender: linux-kernel-owner@vger.kernel.org
Precedence: bulk
List-ID: <linux-kernel.vger.kernel.org>
X-Mailing-List: linux-kernel@vger.kernel.org

> On Sep 3, 2019, at 8:17 AM, Dave Hansen <dave.hansen@intel.com> wrote:
>=20
> On 8/23/19 3:52 PM, Nadav Amit wrote:
>> n_pages		concurrent	+deferred-pti		change
>> -------		----------	-------------		------
>> 1		2119		1986 			-6.7%
>> 10		6791		5417 			 -20%
>>=20
>> Please let me know if I missed something that affects security or
>> performance.
>=20
> Hi Nadav,
>=20
> Is this in a VM or on bare metal?  Could you also share the bare
> /proc/cpuinfo for one of the CPU threads?  I want to make sure that any
> oddities in the stepping or microcode are known.

Bare-metal. Note that some of the benefit does come from having tighter
loops for INVPCID/INVLPG, but the big difference is due to INVPCID being
slower.

I am kind of surprised that you are surprised. I was under the impression
that INVPCID-single lower performance is known. Let me know if I did
something wrong.

processor	: 55
vendor_id	: GenuineIntel
cpu family	: 6
model		: 79
model name	: Intel(R) Xeon(R) CPU E5-2660 v4 @ 2.00GHz
stepping	: 1
microcode	: 0xb000036
cpu MHz		: 2403.035
cache size	: 35840 KB
physical id	: 1
siblings	: 28
core id		: 14
cpu cores	: 14
apicid		: 61
initial apicid	: 61
fpu		: yes
fpu_exception	: yes
cpuid level	: 20
wp		: yes
flags		: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat =
pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rd=
tscp lm constant_tsc arch_perfmon pebs bts rep_good nopl xtopology nonstop_=
tsc cpuid aperfmperf pni pclmulqdq dtes64 monitor ds_cpl vmx smx est tm2 ss=
se3 sdbg fma cx16 xtpr pdcm pcid dca sse4_1 sse4_2 x2apic movbe popcnt tsc_=
deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fa=
ult epb cat_l3 cdp_l3 invpcid_single pti ssbd ibrs ibpb stibp tpr_shadow vn=
mi flexpriority ept vpid fsgsbase tsc_adjust bmi1 hle avx2 smep bmi2 erms i=
nvpcid rtm cqm rdt_a rdseed adx smap intel_pt xsaveopt cqm_llc cqm_occup_ll=
c cqm_mbm_total cqm_mbm_local dtherm ida arat pln pts md_clear flush_l1d
bugs		: cpu_meltdown spectre_v1 spectre_v2 spec_store_bypass l1tf mds swapg=
s
bogomips	: 4001.56
clflush size	: 64
cache_alignment	: 64
address sizes	: 46 bits physical, 48 bits virtual
power management: