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From:   Leonard Crestez <leonard.crestez@nxp.com>
To:     Anson Huang <anson.huang@nxp.com>, Abel Vesa <abel.vesa@nxp.com>,
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Subject: Re: [PATCH 1/2] clk: imx8mm: Move 1443X/1416X PLL clock structure to
 common place
Thread-Topic: [PATCH 1/2] clk: imx8mm: Move 1443X/1416X PLL clock structure to
 common place
Thread-Index: AQHVY9Cav3A/XqpohU+k0poiSHpABg==
Date:   Thu, 5 Sep 2019 13:05:11 +0000
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On 05.09.2019 12:59, Anson Huang wrote:=0A=
> Many i.MX8M SoCs use same 1443X/1416X PLL, such as i.MX8MM,=0A=
> i.MX8MN and later i.MX8M SoCs, moving these PLL definitions=0A=
> to common place can save a lot of duplicated code on each=0A=
> platform.=0A=
=0A=
There are lots of similarities between imx8m clocks, do you plan to do =0A=
combine them further?=0A=
=0A=
> Meanwhile, no need to define PLL clock structure for every=0A=
> module which uses same type of PLL, e.g., audio/video/dram use=0A=
> 1443X PLL, arm/gpu/vpu/sys use 1416X PLL, define 2 PLL clock=0A=
> structure for each group is enough.=0A=
=0A=
> diff --git a/drivers/clk/imx/clk.c b/drivers/clk/imx/clk.c=0A=
=0A=
> +const struct imx_pll14xx_rate_table imx_pll1416x_tbl[] =3D {=0A=
> +	PLL_1416X_RATE(1800000000U, 225, 3, 0),=0A=
> +	PLL_1416X_RATE(1600000000U, 200, 3, 0),=0A=
> +	PLL_1416X_RATE(1200000000U, 300, 3, 1),=0A=
> +	PLL_1416X_RATE(1000000000U, 250, 3, 1),=0A=
> +	PLL_1416X_RATE(800000000U,  200, 3, 1),=0A=
> +	PLL_1416X_RATE(750000000U,  250, 2, 2),=0A=
> +	PLL_1416X_RATE(700000000U,  350, 3, 2),=0A=
> +	PLL_1416X_RATE(600000000U,  300, 3, 2),=0A=
> +};=0A=
> +=0A=
> +const struct imx_pll14xx_rate_table imx_pll1443x_tbl[] =3D {=0A=
> +	PLL_1443X_RATE(650000000U, 325, 3, 2, 0),=0A=
> +	PLL_1443X_RATE(594000000U, 198, 2, 2, 0),=0A=
> +	PLL_1443X_RATE(393216000U, 262, 2, 3, 9437),=0A=
> +	PLL_1443X_RATE(361267200U, 361, 3, 3, 17511),=0A=
> +};=0A=
> +=0A=
> +struct imx_pll14xx_clk imx_1443x_pll =3D {=0A=
> +	.type =3D PLL_1443X,=0A=
> +	.rate_table =3D imx_pll1443x_tbl,=0A=
> +	.rate_count =3D ARRAY_SIZE(imx_pll1443x_tbl),=0A=
> +};=0A=
> +=0A=
> +struct imx_pll14xx_clk imx_1416x_pll =3D {=0A=
> +	.type =3D PLL_1416X,=0A=
> +	.rate_table =3D imx_pll1416x_tbl,=0A=
> +	.rate_count =3D ARRAY_SIZE(imx_pll1416x_tbl),=0A=
> +};=0A=
=0A=
Perhaps these consts should be in clk-pll14xx.c? That way they won't be =0A=
compiled for imx6 as well.=0A=
=0A=
--=0A=
Regards,=0A=
Leonard=0A=