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Fri, 6 Sep 2019 09:12:14 +0000 From: Chester Lin To: Anup Patel CC: Chester Lin , "rick@andestech.com" , "merker@debian.org" , "aou@eecs.berkeley.edu" , "marek.vasut@gmail.com" , "tglx@linutronix.de" , "linux-riscv@lists.infradead.org" , "palmer@sifive.com" , "paul.walmsley@sifive.com" , "linux-kernel@vger.kernel.org" , "Anup.Patel@wdc.com" , "atish.patra@wdc.com" Subject: Re: [PATCH] riscv: save space on the magic number field of image header Thread-Topic: [PATCH] riscv: save space on the magic number field of image header Thread-Index: AQHVZIMcNduMKr0kk0WFNI6AGCbw56ceTwPLgAAOM4A= Date: Fri, 6 Sep 2019 09:12:14 +0000 Message-ID: <20190906091151.GA311@linux-8mug> References: <20190906071631.23695-1-clin@suse.com> In-Reply-To: Accept-Language: zh-TW, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK2PR04CA0053.apcprd04.prod.outlook.com (2603:1096:202:14::21) To BY5PR18MB3283.namprd18.prod.outlook.com (2603:10b6:a03:196::11) authentication-results: spf=none (sender IP is ) smtp.mailfrom=clin@suse.com; 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received-spf: None (protection.outlook.com: suse.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: cC0g4g0hBbfKM+O/bHgZbIQ5nDsnHa418cDhBtoVD/Il7eBHeQaY90PlB+05G7pAi/DAfYSBDXCf22t/ORfBbqw/Ghd2kruMfvqO9L/RFYv+h9CObj+D4v5ZpxkGoLhfEonfURX2Lwv9NFj8aJah72MZyB731SerlUDw+I3giHM62H4AZ/ovcDxb6IconA1IMhWa/3BcTfd+/+r3Hbbn8rls1WxHogzNEKSHK8+FLbzljyvLtj435CkhjrJ7VdYnDUwhS+6WdLQwOTRCBr7ZC2T+1SogsJOAKb2jccttS2ivwm4egBgo1uy3BdYXNfsnUOy78fDjoR0XYEBQQ+6qFJEHivWdTNCqR3jAKGXUv5EzzmU0KXS1y43NUj27+x6+wPNTPED6rMR/hlO5SYg4kXzL1xZF5/tTnM2W4LszjWM= Content-Type: text/plain; charset="us-ascii" Content-ID: Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 5008b175-4fca-4779-f6d8-08d732aa4eca X-MS-Exchange-CrossTenant-originalarrivaltime: 06 Sep 2019 09:12:14.6966 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 856b813c-16e5-49a5-85ec-6f081e13b527 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: lUwzKfJfJvOZAHdNEmyd5zV8S64t4tWn8gPg4N7rINsReDuNmh/t3tVUExi/Xuzm X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR18MB3172 X-OriginatorOrg: suse.com Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Anup, On Fri, Sep 06, 2019 at 01:50:37PM +0530, Anup Patel wrote: > On Fri, Sep 6, 2019 at 12:50 PM Chester Lin wrote: > > > > Change the symbol from "RISCV" to "RSCV" so the magic number can be 32-bit > > long, which is consistent with other architectures. > > > > Signed-off-by: Chester Lin > > --- > > arch/riscv/include/asm/image.h | 9 +++++---- > > arch/riscv/kernel/head.S | 5 ++--- > > 2 files changed, 7 insertions(+), 7 deletions(-) > > > > diff --git a/arch/riscv/include/asm/image.h b/arch/riscv/include/asm/image.h > > index ef28e106f247..ec8bbfe86dde 100644 > > --- a/arch/riscv/include/asm/image.h > > +++ b/arch/riscv/include/asm/image.h > > @@ -3,7 +3,8 @@ > > #ifndef __ASM_IMAGE_H > > #define __ASM_IMAGE_H > > > > -#define RISCV_IMAGE_MAGIC "RISCV" > > +#define RISCV_IMAGE_MAGIC "RSCV" > > + > > > > #define RISCV_IMAGE_FLAG_BE_SHIFT 0 > > #define RISCV_IMAGE_FLAG_BE_MASK 0x1 > > @@ -39,9 +40,9 @@ > > * @version: version > > * @res1: reserved > > * @res2: reserved > > - * @magic: Magic number > > * @res3: reserved (will be used for additional RISC-V specific > > * header) > > + * @magic: Magic number > > * @res4: reserved (will be used for PE COFF offset) > > * > > * The intention is for this header format to be shared between multiple > > @@ -57,8 +58,8 @@ struct riscv_image_header { > > u32 version; > > u32 res1; > > u64 res2; > > - u64 magic; > > - u32 res3; > > + u64 res3; > > + u32 magic; > > u32 res4; > > }; > > #endif /* __ASSEMBLY__ */ > > diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S > > index 0f1ba17e476f..1f8fffbecf68 100644 > > --- a/arch/riscv/kernel/head.S > > +++ b/arch/riscv/kernel/head.S > > @@ -39,9 +39,8 @@ ENTRY(_start) > > .word RISCV_HEADER_VERSION > > .word 0 > > .dword 0 > > - .asciz RISCV_IMAGE_MAGIC > > - .word 0 > > - .balign 4 > > + .dword 0 > > + .ascii RISCV_IMAGE_MAGIC > > .word 0 > > > > .global _start_kernel > > -- > > 2.22.0 > > > > This change is not at all backward compatible with > existing booti implementation in U-Boot. > > It changes: > 1. Magic offset > 2. Magic value itself > Thank you for the reminder. I have submitted a patch to U-Boot as well. Since my email post to the uboot mailing list is still under review by the list moderator, here I just list my code change of uboot: diff --git a/arch/riscv/lib/image.c b/arch/riscv/lib/image.c index d063beb7df..e8a8cb7190 100644 --- a/arch/riscv/lib/image.c +++ b/arch/riscv/lib/image.c @@ -14,8 +14,8 @@ DECLARE_GLOBAL_DATA_PTR; -/* ASCII version of "RISCV" defined in Linux kernel */ -#define LINUX_RISCV_IMAGE_MAGIC 0x5643534952 +/* ASCII version of "RSCV" defined in Linux kernel */ +#define LINUX_RISCV_IMAGE_MAGIC 0x56435352 struct linux_image_h { uint32_t code0; /* Executable code */ @@ -25,8 +25,8 @@ struct linux_image_h { uint64_t res1; /* reserved */ uint64_t res2; /* reserved */ uint64_t res3; /* reserved */ - uint64_t magic; /* Magic number */ - uint32_t res4; /* reserved */ + uint64_t res4; /* reserved */ + uint32_t magic; /* Magic number */ uint32_t res5; /* reserved */ }; > We don't see this header changing much apart from > res1/res2 becoming flags in-future. The PE COFF header > will be append to this header in-future and it will have lot > more information. > I think a smaller magic field will let res4 have more room [32bit->64bit], which could offer more options for RISC-V's boot-flow development in the future. This change also synchronizes with arm64's image header. > Regards, > Anup >