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Subject: Re: [PATCH v5 1/4] dt-bindings: EDAC: Add Amazon's Annapurna Labs L1
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To:     Rob Herring <robh@kernel.org>
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From:   James Morse <james.morse@arm.com>
Message-ID: <21050550-7629-e8f7-2d30-16c1858cf3cc@arm.com>
Date:   Fri, 6 Sep 2019 17:28:59 +0100
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Hi Rob,

On 30/08/2019 22:50, Rob Herring wrote:
> So KVM provides a semi-CortexA57? Code that runs on real h/w won't as a guest.

KVM provides the architectural bits of Cortex-A57's EL1, when running on A57.

Code that depends on EL2, won't run as a guest. Code that depends on some
non-architectural behaviour of A57 won't work in a guest, (e.g. the PMU)
Features the hypervisor doesn't completely support may get hidden. The aim is to provide
an virtual CPU, it might not be exactly the same as the one you're running on.

Hypervisors have to disable access to the imp-def registers as they may allow the guest to
break its confinement. (e.g. messing with the L2 timing)

Code using imp-def instructions at EL1 needs to know they aren't trapped/disabled by a
higher exception level. If someone wants to emulate these, something would need a model of
what those imp-def instructions do.


Thanks,

James