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[209.132.180.67]) by mx.google.com with ESMTP id q16si8717643pff.181.2019.09.07.06.47.21; Sat, 07 Sep 2019 06:48:06 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@googlemail.com header.s=20161025 header.b=S03AX30p; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=googlemail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2406017AbfIFRRY (ORCPT + 99 others); Fri, 6 Sep 2019 13:17:24 -0400 Received: from mail-ot1-f65.google.com ([209.85.210.65]:45570 "EHLO mail-ot1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391459AbfIFRRX (ORCPT ); Fri, 6 Sep 2019 13:17:23 -0400 Received: by mail-ot1-f65.google.com with SMTP id 41so2602948oti.12; Fri, 06 Sep 2019 10:17:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=9evHry1UrtWiGWxeLaRDwMC+G1/K0C5Wqdz0SlRBtRA=; b=S03AX30pGa/riu4c+Jmvw31thlqCJ6/58BYW5EDstl8tut2pIX6DS+XKqBIPly98j0 arM5bAlXCV9be8gl83690pSpmR1J9dMDi2ACleKB3PCN5J9KZL6g5iAoRmxWbMiqvNF3 qC3itT8bwqPnQpFTXFxeLKOfYW+dUY5c8Ct8IOQFoscT2ROpSB17Myo1f6++Q3q3E9fp YGPB3qdZDIGk5096953Vhf6t3BQbyOG0UHoqwucW8WvoqVupxW0PUzT6nbVdjrekix1i O6TPhnexuV9aJm6HkgAJNlwlltU27I7emzs4SGZ34QBV1oyDhJrvrzc/OMHGJmk+Mg+o HEvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=9evHry1UrtWiGWxeLaRDwMC+G1/K0C5Wqdz0SlRBtRA=; b=GZ/IPlsfDs05a2d9jg5rDFN55JR6lH7JbywClAN6a64YkubQBRsq1DQM8V+gkputfR 6SDxjto03hnwz4cZNWHLlXpUk4FOD5BL/xJVBujqLkODhkJDaZdVZRzzmaYQRmVELy46 L8wrDLlD/oBlLWJ8sw6Vudl2fzdx40yGv8la22g80Mv4CSuD5516p2+ssOkx1cLxhc2s OReOy0E3Rxzm3NhJ4xNi+pHRJELNLAsMnQm1KAE6CwhEIo4By6RFbGmo3pAIL0nRvEgh +hyYRMfrboso/yr1jSP09xXR/VGGt7VSwS0e/5tQRlbOcokRnJMMH1vkoNCu2/RJjmb/ 7JaQ== X-Gm-Message-State: APjAAAWfhXc4VhLY8S/XZlS+R07PTRTn2MD/rZCCCBhcTaRmUpRKzh0J 5xHBOG35rKQh9KdPdVIeYMIzCQ3LUBS+gBYvvtA= X-Received: by 2002:a05:6830:1e5a:: with SMTP id e26mr7852824otj.96.1567790242296; Fri, 06 Sep 2019 10:17:22 -0700 (PDT) MIME-Version: 1.0 References: In-Reply-To: From: Martin Blumenstingl Date: Fri, 6 Sep 2019 19:17:11 +0200 Message-ID: Subject: Re: [PATCH v3 1/2] dt-bindings: PCI: intel: Add YAML schemas for the PCIe RC controller To: "Chuan Hua, Lei" Cc: Dilip Kota , jingoohan1@gmail.com, gustavo.pimentel@synopsys.com, lorenzo.pieralisi@arm.com, robh@kernel.org, linux-pci@vger.kernel.org, hch@infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, andriy.shevchenko@intel.com, cheol.yong.kim@intel.com, qi-ming.wu@intel.com Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Sep 6, 2019 at 5:22 AM Chuan Hua, Lei wrote: [...] > >> +examples: > >> + - | > >> + pcie10:pcie@d0e00000 { > >> + compatible = "intel,lgm-pcie"; > >> + device_type = "pci"; > >> + #address-cells = <3>; > >> + #size-cells = <2>; > >> + reg = < > >> + 0xd0e00000 0x1000 > >> + 0xd2000000 0x800000 > >> + 0xd0a41000 0x1000 > >> + >; > >> + reg-names = "dbi", "config", "app"; > >> + linux,pci-domain = <0>; > >> + max-link-speed = <4>; > >> + bus-range = <0x00 0x08>; > >> + interrupt-parent = <&ioapic1>; > >> + interrupts = <67 1>; > >> + #interrupt-cells = <1>; > >> + interrupt-map-mask = <0 0 0 0x7>; > >> + interrupt-map = <0 0 0 1 &ioapic1 27 1>, > >> + <0 0 0 2 &ioapic1 28 1>, > >> + <0 0 0 3 &ioapic1 29 1>, > >> + <0 0 0 4 &ioapic1 30 1>; > > is the "1" in the interrupts and interrupt-map properties IRQ_TYPE_EDGE_RISING? > > you can use these macros in this example as well, see > > Documentation/devicetree/bindings/iio/accel/adi,adxl372.yaml for > > example > > No. 1 here means index from arch/x86/devicetree.c > > static struct of_ioapic_type of_ioapic_type[] = > { > { > .out_type = IRQ_TYPE_EDGE_RISING, > .trigger = IOAPIC_EDGE, > .polarity = 1, > }, > { > .out_type = IRQ_TYPE_LEVEL_LOW, > .trigger = IOAPIC_LEVEL, > .polarity = 0, > }, > { > .out_type = IRQ_TYPE_LEVEL_HIGH, > .trigger = IOAPIC_LEVEL, > .polarity = 1, > }, > { > .out_type = IRQ_TYPE_EDGE_FALLING, > .trigger = IOAPIC_EDGE, > .polarity = 0, > }, > }; > > static int dt_irqdomain_alloc(struct irq_domain *domain, unsigned int virq, > unsigned int nr_irqs, void *arg) > { > struct irq_fwspec *fwspec = (struct irq_fwspec *)arg; > struct of_ioapic_type *it; > struct irq_alloc_info tmp; > int type_index; > > if (WARN_ON(fwspec->param_count < 2)) > return -EINVAL; > > type_index = fwspec->param[1]; // index. > if (type_index >= ARRAY_SIZE(of_ioapic_type)) > return -EINVAL; > > I would not see this definition is user-friendly. But it is how x86 > handles at the moment. thank you for explaining this - I had no idea x86 is different from all other platforms I know the only upstream x86 .dts I could find (arch/x86/platform/ce4100/falconfalls.dts) also uses the magic x86 numbers so I'm fine with this until someone else knows a better solution Martin