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[209.132.180.67]) by mx.google.com with ESMTP id k5si5715295eds.116.2019.09.08.13.48.10; Sun, 08 Sep 2019 13:48:34 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@googlemail.com header.s=20161025 header.b=TtZYR2EF; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=googlemail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2406066AbfIGPCS (ORCPT + 99 others); Sat, 7 Sep 2019 11:02:18 -0400 Received: from mail-ot1-f66.google.com ([209.85.210.66]:43132 "EHLO mail-ot1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391215AbfIGPCS (ORCPT ); Sat, 7 Sep 2019 11:02:18 -0400 Received: by mail-ot1-f66.google.com with SMTP id b2so8504710otq.10; Sat, 07 Sep 2019 08:02:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=googlemail.com; s=20161025; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=vQuUa7SD4x8TPRd4rEMdVFipQdAElSjSwWznDJwYZRs=; b=TtZYR2EFApgjge1T6n3joQtpMqyYmTxuLma+kCVNN7wn/Td2sozX4uMMJyJOBh7cW4 kuejU+OweVVkrAGmTKoS9jy8O7VSEzhwrKsu/XQYz4JGiLlb4/v9Oj2K61iItcV03uxD XGbdCpzAYDZDHIfItszdiml7ALRrPBQy7oYrMe1M0q9v5OmefhcPQP6bdBjS2OFHuIHp s2aIyVQhQV7q5e5QDOqkOc5hFXeTww48b2ucrRtyI2y5k+8+dElAjTG39dpzMzVHV+ZF 8mGjwrC0tO9qU5v86blecaWHXjKJC2KfzoeW8mWAmuyr6tKzygm8r2rBxPtqpw1GAF8z ByfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=vQuUa7SD4x8TPRd4rEMdVFipQdAElSjSwWznDJwYZRs=; b=b0l7Rd5eJHMRAw5GyE2p+BAv99UVQQHRVLuwARkAHjabdqYJ4KyU+KdLUsh0oMh+Wu 6HwZ6ilvHbXYYXdzegOZiIRm6po/cO8GyAurfI2QaWpVPSXS71EfciIt80v7nebsrnq5 5dUrpud8ETgRQNYlSJJJxMdHnBFIQVe+KLBDTujFbUAbUz8tEzdi/pfXfp9cjapfI2qw x5Yv3VY4Ulb2BSqsE5oB9AyYOlWpbKtRG77XY/Cjy69blUB6nVxcZYZJEnPlW2ohlL1b lOF2L0t0mY+05pnC2Bm59F7+xbIVi3wwsEzu1a3wpuOZBfDSjZYmMxIsMSXyfRrWv76J RFRA== X-Gm-Message-State: APjAAAW0LE3wJCn7sCO1jrHI+8Bb9S9eH7R1zkwQipOwuateUZBJh4qj GcRl1dYep7hEELnkNShfiBmNyLNsKJ143m6gCSs= X-Received: by 2002:a9d:5c0f:: with SMTP id o15mr12429347otk.81.1567868537282; Sat, 07 Sep 2019 08:02:17 -0700 (PDT) MIME-Version: 1.0 References: <1567667251-33466-1-git-send-email-jianxin.pan@amlogic.com> <1567667251-33466-5-git-send-email-jianxin.pan@amlogic.com> In-Reply-To: From: Martin Blumenstingl Date: Sat, 7 Sep 2019 17:02:06 +0200 Message-ID: Subject: Re: [PATCH v2 4/4] arm64: dts: add support for A1 based Amlogic AD401 To: Jianxin Pan Cc: Kevin Hilman , linux-amlogic@lists.infradead.org, Rob Herring , Carlo Caione , Neil Armstrong , Jerome Brunet , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jian Hu , Hanjie Lin , Xingyu Chen , Victor Wan , Qiufang Dai , Tao Zeng Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jianxin, On Fri, Sep 6, 2019 at 7:58 AM Jianxin Pan wrote: [...] > > also I'm a bit surprised to see no busses (like aobus, cbus, periphs, ...) here > > aren't there any busses defined in the A1 SoC implementation or are > > were you planning to add them later? > Unlike previous series,there is no Cortex-M3 AO CPU in A1, and there is no AO/EE power domain. > Most of the registers are on the apb_32b bus. aobus, cbus and periphs are not used in A1. OK, thank you for the explanation since you're going to re-send the patch anyways: can you please include the apb_32b bus? all other upstream Amlogic .dts are using the bus definitions, so that will make A1 consistent with the other SoCs Martin