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Cc:     bjorn.andersson@linaro.org, niklas.cassel@linaro.org,
        linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
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To:     agross@kernel.org, jorge.ramirez-ortiz@linaro.org,
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From:   Stephen Boyd <sboyd@kernel.org>
Subject: Re: [PATCH 2/5] clk: qcom: apcs-msm8916: get parent clock names from DT
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Date:   Mon, 09 Sep 2019 03:21:16 -0700
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Quoting Jorge Ramirez-Ortiz (2019-08-26 09:45:07)
> @@ -76,10 +88,11 @@ static int qcom_apcs_msm8916_clk_probe(struct platfor=
m_device *pdev)
>         a53cc->src_shift =3D 8;
>         a53cc->parent_map =3D gpll0_a53cc_map;
> =20
> -       a53cc->pclk =3D devm_clk_get(parent, NULL);
> +       a53cc->pclk =3D of_clk_get(parent->of_node, pll_index);

Presumably the PLL was always index 0, so why are we changing it to
index 1 sometimes? Seems unnecessary.