Received: by 2002:a25:c593:0:0:0:0:0 with SMTP id v141csp4957246ybe; Mon, 9 Sep 2019 18:04:43 -0700 (PDT) X-Google-Smtp-Source: APXvYqycTJ+ylaYCVEpWbZhujIBbnDR+oMnpe3NP0tWgjg93Dcc26JpERE3FVMzPVtl8BWmcW9kh X-Received: by 2002:aa7:c355:: with SMTP id j21mr27031049edr.210.1568077483813; Mon, 09 Sep 2019 18:04:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1568077483; cv=none; d=google.com; s=arc-20160816; b=oBOP/ZeFwHANwbow8yv7v+kgVrUM26Rm8atZU0VqJc14een/jH24dv1UruYIm1ee+l rFFOmkAxfJhnhJwPQcLcYEdJX+L0Xp00Cn/8sr2631dRJdTjQW6LWXryTz7OXii5XI7S PDBjEloQI6xvpaKUyzq24HQtekiwjkC0k5CCoCl55gq25YFNHAR68f9OSdthstIJjvxG Y5zMYVr3bVVKQIAPsvOKo+gjsFPQpRLu6+tzN9GS/sKHpxD/umOg5o8XjMCojDHG9CVO OO1X5kB0S7x5ACaAUhoiCZ4yTIB2XaI7ZiWH+og29pt/pyr6rtVV/yqXg3Fnb6WZ0hhC o7zA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding :content-language:in-reply-to:mime-version:user-agent:date :message-id:from:references:cc:to:subject; bh=wuEqhLif78+hPUxGd0vs/zoKs1HQWhOzkODYwuIiwHY=; b=du5RrGq4a9AvNz6NW4fRS1Yt69IInolurUwpy5dAMwpmY/Xv3b4UKnwkxhJTGKzAxU W6Fzc2QmWZQQXbfKgUqOaNykzG24P21+4dpdq3bzstZQPOLfoWeg6SvI2gNPyInNBpN6 OvHiT5i+iH2IWZDvXZqUNLyzUEs1hSAUBmFKz06o03dbRcylHtHJcp5VDZzaYwy1eVWZ RZ4ypWH9vdSDY2ZpPZvWA6GPjI2BWcJ+HOZ2nxXT7IMUU18fAkCpNZHCsa56LLyCCZHQ 1hwScErUmPD0gta2GJfYKlN1bGC4CKOm0dQ3L/H31yy5BSeD77fvU14gCXY/Oe6DwrNe z6Ig== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id nm3si8490911ejb.310.2019.09.09.18.04.19; Mon, 09 Sep 2019 18:04:43 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2404651AbfIIMDi (ORCPT + 99 others); Mon, 9 Sep 2019 08:03:38 -0400 Received: from mail-sh.amlogic.com ([58.32.228.43]:48752 "EHLO mail-sh.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2404215AbfIIMDi (ORCPT ); Mon, 9 Sep 2019 08:03:38 -0400 Received: from [10.18.29.226] (10.18.29.226) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1591.10; Mon, 9 Sep 2019 20:04:28 +0800 Subject: Re: [PATCH v2 4/4] arm64: dts: add support for A1 based Amlogic AD401 To: Martin Blumenstingl CC: Kevin Hilman , , Rob Herring , Carlo Caione , Neil Armstrong , Jerome Brunet , , , , Jian Hu , Hanjie Lin , Xingyu Chen , Victor Wan , Qiufang Dai , Tao Zeng References: <1567667251-33466-1-git-send-email-jianxin.pan@amlogic.com> <1567667251-33466-5-git-send-email-jianxin.pan@amlogic.com> From: Jianxin Pan Message-ID: Date: Mon, 9 Sep 2019 20:04:27 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.18.29.226] X-ClientProxiedBy: mail-sh.amlogic.com (10.18.11.5) To mail-sh.amlogic.com (10.18.11.5) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Martin, On 2019/9/7 23:02, Martin Blumenstingl wrote: > Hi Jianxin, > > On Fri, Sep 6, 2019 at 7:58 AM Jianxin Pan wrote: > [...] >>> also I'm a bit surprised to see no busses (like aobus, cbus, periphs, ...) here >>> aren't there any busses defined in the A1 SoC implementation or are >>> were you planning to add them later? >> Unlike previous series,there is no Cortex-M3 AO CPU in A1, and there is no AO/EE power domain. >> Most of the registers are on the apb_32b bus. aobus, cbus and periphs are not used in A1. > OK, thank you for the explanation > since you're going to re-send the patch anyways: can you please > include the apb_32b bus? > all other upstream Amlogic .dts are using the bus definitions, so that > will make A1 consistent with the other SoCs In A1 (and the later C1), BUS is not mentioned in the memmap and register spec. Registers are organized and grouped by functions, and we can not find information about buses from the SoC document. Maybe it's better to remove bus definitions for these chips. > > > Martin > > . >