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[209.132.180.67]) by mx.google.com with ESMTP id q46si10337515eda.44.2019.09.10.05.14.54; Tue, 10 Sep 2019 05:15:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@sifive.com header.s=google header.b=ljRKsul0; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2391430AbfIJJwp (ORCPT + 99 others); Tue, 10 Sep 2019 05:52:45 -0400 Received: from mail-lf1-f65.google.com ([209.85.167.65]:34994 "EHLO mail-lf1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S2391369AbfIJJwp (ORCPT ); Tue, 10 Sep 2019 05:52:45 -0400 Received: by mail-lf1-f65.google.com with SMTP id w6so12959042lfl.2 for ; Tue, 10 Sep 2019 02:52:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=UCCxiazzNKm8GfRdBMzix7RqbnKVVm8PwfIPcf8Ud9o=; b=ljRKsul0mZVE7hjuRdwu0vDFTakT8JFE/2cyerU5FPgdhHWt1rkLc/XVmzFSuCdPyA /G3lIV76GIKLQb3bB+uKUlq6zEOJp1/Jn7Bscc2/jQI6vtCMBKWUsj/fmMSyCEd2qNAL V1vG8Se1hHXhwDqAbg8s7vDI3Ibg8uD2ZzkbbiS48Sm3gFFKFoG/OpoGBsMLp+jl42NB CX+IqlW87dKEJnQTPMd2wc1doUzIXECqEdcQZZhRlbagUPN5NRb3QL2t3CHNXtubY7Qk qdl1LrhsmO8b1M0BjYMm7Z3hO+0+IS7IDQImB+80dHHcpeWxrs8aFoFmvgFMCl1SsLZg yH/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=UCCxiazzNKm8GfRdBMzix7RqbnKVVm8PwfIPcf8Ud9o=; b=Gg6WLshm2jpTtwSkBnMocf6Vv6RIRbdU9tTm9EsYuQwbwMA1W1gj5zD1nqlvP776F5 UsleVncq2KMG43dsCZq3NPe4CRUGw0VMqT+ioPnjMvUJOm1AoWKeq5+xKR0oHDKR4QhI 8c7JYDDNpc81XdjYgODFMI1fjDU4vB4cmVVv63HdCFfjD6W9aPEVSSJvjGVQK7lkctxw 45v4cVHL29qnltBYsmsqN0XiafqQ3e7xlKDqecRSzJlLs9805REJYJbUITuHHEakymK/ K1gmPv2ql1OwF94hQgE0JEqmRkmkXXyWKAKZQYH2ut8aPZhwz8Zd/sOLZWTuoQqCw56w uv2w== X-Gm-Message-State: APjAAAUCb19qhurx474d6ilHtIUGvbhuM11q99rt26GBiSAfy39Ixk/Q BHTWAH8uBkdupc8B0ERTyMQD29KqJn63Uo7sJFu7oEPM X-Received: by 2002:a19:770a:: with SMTP id s10mr2194571lfc.30.1568109163186; Tue, 10 Sep 2019 02:52:43 -0700 (PDT) MIME-Version: 1.0 References: <1566379420-26762-1-git-send-email-yash.shah@sifive.com> In-Reply-To: <1566379420-26762-1-git-send-email-yash.shah@sifive.com> From: Yash Shah Date: Tue, 10 Sep 2019 15:22:07 +0530 Message-ID: Subject: Re: [PATCH] riscv: dts: Add DT support for SiFive FU540 PWM driver To: Rob Herring , Mark Rutland , Paul Walmsley Cc: Palmer Dabbelt , Albert Ou , Bin Meng , Sagar Kadam , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, "linux-kernel@vger.kernel.org List" , Sachin Ghadi Content-Type: text/plain; charset="UTF-8" Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Any comments on this patch? - Yash On Wed, Aug 21, 2019 at 2:53 PM Yash Shah wrote: > > Add the PWM DT node in SiFive FU540 soc-specific DT file. > Enable the PWM nodes in HiFive Unleashed board-specific DT file. > > Signed-off-by: Yash Shah > --- > arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 19 +++++++++++++++++++ > arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts | 8 ++++++++ > 2 files changed, 27 insertions(+) > > diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi > index 42b5ec2..bb422db 100644 > --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi > +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi > @@ -230,6 +230,25 @@ > #size-cells = <0>; > status = "disabled"; > }; > + pwm0: pwm@10020000 { > + compatible = "sifive,pwm0"; > + reg = <0x0 0x10020000 0x0 0x1000>; > + interrupt-parent = <&plic0>; > + interrupts = <42 43 44 45>; > + clocks = <&prci PRCI_CLK_TLCLK>; > + #pwm-cells = <3>; > + status = "disabled"; > + }; > + pwm1: pwm@10021000 { > + compatible = "sifive,pwm0"; > + reg = <0x0 0x10021000 0x0 0x1000>; > + interrupt-parent = <&plic0>; > + interrupts = <46 47 48 49>; > + reg-names = "control"; > + clocks = <&prci PRCI_CLK_TLCLK>; > + #pwm-cells = <3>; > + status = "disabled"; > + }; > > }; > }; > diff --git a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts > index 93d68cb..104d334 100644 > --- a/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts > +++ b/arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dts > @@ -85,3 +85,11 @@ > reg = <0>; > }; > }; > + > +&pwm0 { > + status = "okay"; > +}; > + > +&pwm1 { > + status = "okay"; > +}; > -- > 1.9.1 >