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From:   <Eugen.Hristev@microchip.com>
To:     <mturquette@baylibre.com>, <sboyd@kernel.org>,
        <alexandre.belloni@bootlin.com>, <linux-clk@vger.kernel.org>,
        <linux-arm-kernel@lists.infradead.org>,
        <linux-kernel@vger.kernel.org>
CC:     <Nicolas.Ferre@microchip.com>, <Ludovic.Desroches@microchip.com>,
        <Eugen.Hristev@microchip.com>
Subject: [PATCH 2/2] clk: at91: select parent if main oscillator or bypass is
 enabled
Thread-Topic: [PATCH 2/2] clk: at91: select parent if main oscillator or
 bypass is enabled
Thread-Index: AQHVZyOF1aEN8SUUrUGnVcaoCs40gw==
Date:   Mon, 9 Sep 2019 15:30:34 +0000
Message-ID: <1568042692-11784-2-git-send-email-eugen.hristev@microchip.com>
References: <1568042692-11784-1-git-send-email-eugen.hristev@microchip.com>
In-Reply-To: <1568042692-11784-1-git-send-email-eugen.hristev@microchip.com>
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From: Eugen Hristev <eugen.hristev@microchip.com>

Selecting the right parent for the main clock is done using only
main oscillator enabled bit.
In case we have this oscillator bypassed by an external signal (no driving
on the XOUT line), we still use external clock, but with BYPASS bit set.
So, in this case we must select the same parent as before.
Create a macro that will select the right parent considering both bits from
the MOR register.
Use this macro when looking for the right parent.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
---
 drivers/clk/at91/clk-main.c | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c
index ebe9b99..87083b3 100644
--- a/drivers/clk/at91/clk-main.c
+++ b/drivers/clk/at91/clk-main.c
@@ -21,6 +21,10 @@
=20
 #define MOR_KEY_MASK		(0xff << 16)
=20
+#define clk_main_parent_select(s)	(((s) & \
+					(AT91_PMC_MOSCEN | \
+					AT91_PMC_OSCBYPASS)) ? 1 : 0)
+
 struct clk_main_osc {
 	struct clk_hw hw;
 	struct regmap *regmap;
@@ -113,7 +117,7 @@ static int clk_main_osc_is_prepared(struct clk_hw *hw)
=20
 	regmap_read(regmap, AT91_PMC_SR, &status);
=20
-	return (status & AT91_PMC_MOSCS) && (tmp & AT91_PMC_MOSCEN);
+	return (status & AT91_PMC_MOSCS) && clk_main_parent_select(tmp);
 }
=20
 static const struct clk_ops main_osc_ops =3D {
@@ -450,7 +454,7 @@ static u8 clk_sam9x5_main_get_parent(struct clk_hw *hw)
=20
 	regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status);
=20
-	return status & AT91_PMC_MOSCEN ? 1 : 0;
+	return clk_main_parent_select(status);
 }
=20
 static const struct clk_ops sam9x5_main_ops =3D {
@@ -492,7 +496,7 @@ at91_clk_register_sam9x5_main(struct regmap *regmap,
 	clkmain->hw.init =3D &init;
 	clkmain->regmap =3D regmap;
 	regmap_read(clkmain->regmap, AT91_CKGR_MOR, &status);
-	clkmain->parent =3D status & AT91_PMC_MOSCEN ? 1 : 0;
+	clkmain->parent =3D clk_main_parent_select(status);
=20
 	hw =3D &clkmain->hw;
 	ret =3D clk_hw_register(NULL, &clkmain->hw);
--=20
2.7.4