Received: by 2002:a25:c593:0:0:0:0:0 with SMTP id v141csp5974564ybe; Tue, 10 Sep 2019 11:34:48 -0700 (PDT) X-Google-Smtp-Source: APXvYqxpXURMJjH16kNMvkzNy2GeEP18HGXS9MkCfO2akcK3tqQaKTcqHW17PLIONB683V/YCHbX X-Received: by 2002:aa7:d28d:: with SMTP id w13mr32099548edq.264.1568140488774; Tue, 10 Sep 2019 11:34:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1568140488; cv=none; d=google.com; s=arc-20160816; b=qdoekuCujOJ+CP6By5lDhX4CAAlErU9rErUoXA3OASq1/eGetSc1vsrDV0fcI2OyKB unWRMjz6aTD9v3vm5rjb1bkwPOdMMfAxGfzuxuzvVGu/9I/DvcP5LGhphJG8AW0H6bUA bSf6NZG0jIZT+UKgR+vEbk5BnRlPHSgdsiCDzeqmAfnCTLGCZwJv3oZqvhqL9uEw73Vr od/cESccBR4qOpGLj1B+DcfpOocUSUNtwtMB46UghEPQh4WAejYxx03JxyE9hMqq+jr5 R3FVexVHZ6zS7r8CsYPBp3Trw8tk3qSm+MYq/VLXoUng2hB51OYFxLPtB5H8TV5TtUW6 DpvQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding :content-language:in-reply-to:mime-version:user-agent:date :message-id:from:references:cc:to:subject; bh=YKh5SrTtnTQdesyD6EM9Pmfqu7Y0dVwb+z25KSKUYlM=; b=sg2cyvIXYZm3Dr+49SNUOmHDjUtZojsSnsYsMM7CCcWjBYeSEU4IDdCatdjiiTOOuQ 6ggoPJTtyhCoDKQHYX93mrRH66qckteO7dkK3IBR5SMFnWCKULSGV/EAfE06xnDoFi7D RYjBKnojUeacwV//VsELWLSX/Zc13w4126p1Vw7jm89m9Spbc8TjQAi5bh51LwsPwopf y1lhQICYrbqU4HTZPRJ0yD77vZVW59QXvErfi9agL3yFu5Tzus0oiaa+knyohMqWl7Gh 5nGTbgS5WN4/aHDzNly+Ng4eb5WTufQ/uYCZGHHJ+mm60hOYZgEmx8ZUXSs1wlWuC4eR bQDA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id f14si11358987edd.134.2019.09.10.11.34.24; Tue, 10 Sep 2019 11:34:48 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729762AbfIIQLn (ORCPT + 99 others); Mon, 9 Sep 2019 12:11:43 -0400 Received: from mail-sh.amlogic.com ([58.32.228.43]:26745 "EHLO mail-sh.amlogic.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726287AbfIIQLn (ORCPT ); Mon, 9 Sep 2019 12:11:43 -0400 Received: from [192.168.0.108] (223.167.21.35) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1591.10; Tue, 10 Sep 2019 00:12:33 +0800 Subject: Re: [PATCH v2 4/4] arm64: dts: add support for A1 based Amlogic AD401 To: Jerome Brunet , Martin Blumenstingl , Kevin Hilman CC: , Neil Armstrong , , , , Jian Hu , Hanjie Lin , Xingyu Chen , Victor Wan , Qiufang Dai , Tao Zeng References: <1567667251-33466-1-git-send-email-jianxin.pan@amlogic.com> <1567667251-33466-5-git-send-email-jianxin.pan@amlogic.com> <1jv9u1ya3o.fsf@starbuckisacylon.baylibre.com> From: Jianxin Pan Message-ID: Date: Tue, 10 Sep 2019 00:12:32 +0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <1jv9u1ya3o.fsf@starbuckisacylon.baylibre.com> Content-Type: text/plain; charset="windows-1252" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [223.167.21.35] X-ClientProxiedBy: mail-sh.amlogic.com (10.18.11.5) To mail-sh.amlogic.com (10.18.11.5) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Jerome, On 2019/9/9 19:36, Jerome Brunet wrote: > > On Sat 07 Sep 2019 at 17:02, Martin Blumenstingl wrote: > >> Hi Jianxin, >> >> On Fri, Sep 6, 2019 at 7:58 AM Jianxin Pan wrote: >> [...] >>>> also I'm a bit surprised to see no busses (like aobus, cbus, periphs, ...) here >>>> aren't there any busses defined in the A1 SoC implementation or are >>>> were you planning to add them later? >>> Unlike previous series,there is no Cortex-M3 AO CPU in A1, and there is no AO/EE power domain. >>> Most of the registers are on the apb_32b bus. aobus, cbus and periphs are not used in A1. >> OK, thank you for the explanation >> since you're going to re-send the patch anyways: can you please >> include the apb_32b bus? > > unless there is an 64 bits apb bus as well, I suppose 'apb' would be enough ? > There is no 64bits apb bus in A1, only apb32. Unlike the previous series, For A1 and C1, we can not get bus information for each register from the memmap and datesheet. Do we need to add bus description for them too? If yes, I can add 'apb' . >> all other upstream Amlogic .dts are using the bus definitions, so that >> will make A1 consistent with the other SoCs >> >> >> Martin > > . >