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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 10 Sep 2019 11:44:22 +0100 Received: from d06av24.portsmouth.uk.ibm.com (d06av24.portsmouth.uk.ibm.com [9.149.105.60]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x8AAiLRt54395070 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 10 Sep 2019 10:44:21 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 742594203F; Tue, 10 Sep 2019 10:44:21 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 144E442045; Tue, 10 Sep 2019 10:44:21 +0000 (GMT) Received: from localhost (unknown [9.85.92.121]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 10 Sep 2019 10:44:20 +0000 (GMT) Date: Tue, 10 Sep 2019 16:14:17 +0530 From: "Naveen N. Rao" Subject: Re: [PATCH 2/2] powerpc/watchpoint: Disable watchpoint hit by larx/stcx instructions To: mikey@neuling.org, mpe@ellerman.id.au, Ravi Bangoria Cc: benh@kernel.crashing.org, christophe.leroy@c-s.fr, linux-kernel@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, paulus@samba.org References: <20190910102422.23233-1-ravi.bangoria@linux.ibm.com> <20190910102422.23233-3-ravi.bangoria@linux.ibm.com> In-Reply-To: <20190910102422.23233-3-ravi.bangoria@linux.ibm.com> MIME-Version: 1.0 User-Agent: astroid/0.15.0 (https://github.com/astroidmail/astroid) Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8BIT X-TM-AS-GCONF: 00 x-cbid: 19091010-0028-0000-0000-0000039A7159 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19091010-0029-0000-0000-0000245CD4A5 Message-Id: <1568111933.eaf72yeuof.naveen@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:,, definitions=2019-09-10_07:,, signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=636 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1906280000 definitions=main-1909100108 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Ravi Bangoria wrote: > If watchpoint exception is generated by larx/stcx instructions, the > reservation created by larx gets lost while handling exception, and > thus stcx instruction always fails. Generally these instructions are > used in a while(1) loop, for example spinlocks. And because stcx > never succeeds, it loops forever and ultimately hangs the system. > > Note that ptrace anyway works in one-shot mode and thus for ptrace > we don't change the behaviour. It's up to ptrace user to take care > of this. > > Signed-off-by: Ravi Bangoria > --- > arch/powerpc/kernel/hw_breakpoint.c | 49 +++++++++++++++++++---------- > 1 file changed, 33 insertions(+), 16 deletions(-) > > diff --git a/arch/powerpc/kernel/hw_breakpoint.c b/arch/powerpc/kernel/hw_breakpoint.c > index 28ad3171bb82..9fa496a598ce 100644 > --- a/arch/powerpc/kernel/hw_breakpoint.c > +++ b/arch/powerpc/kernel/hw_breakpoint.c > @@ -195,14 +195,32 @@ void thread_change_pc(struct task_struct *tsk, struct pt_regs *regs) > tsk->thread.last_hit_ubp = NULL; > } > > +static bool is_larx_stcx_instr(struct pt_regs *regs, unsigned int instr) > +{ > + int ret, type; > + struct instruction_op op; > + > + ret = analyse_instr(&op, regs, instr); > + type = GETTYPE(op.type); > + return (!ret && (type == LARX || type == STCX)); > +} > + > /* > * Handle debug exception notifications. > */ > static bool stepping_handler(struct pt_regs *regs, struct perf_event *bp, > unsigned long addr) > { > - int stepped; > - unsigned int instr; > + unsigned int instr = 0; > + > + if (__get_user_inatomic(instr, (unsigned int *)regs->nip)) > + goto fail; > + > + if (is_larx_stcx_instr(regs, instr)) { > + printk_ratelimited("Watchpoint: Can't emulate/single-step larx/" > + "stcx instructions. Disabling watchpoint.\n"); The below WARN() uses the term 'breakpoint'. Better to use consistent terminology. I would rewrite the above as: printk_ratelimited("Breakpoint hit on instruction that can't be emulated. " "Breakpoint at 0x%lx will be disabled.\n", addr); Otherwise: Acked-by: Naveen N. Rao - Naveen > + goto disable; > + } > > /* Do not emulate user-space instructions, instead single-step them */ > if (user_mode(regs)) { > @@ -211,23 +229,22 @@ static bool stepping_handler(struct pt_regs *regs, struct perf_event *bp, > return false; > } > > - stepped = 0; > - instr = 0; > - if (!__get_user_inatomic(instr, (unsigned int *)regs->nip)) > - stepped = emulate_step(regs, instr); > + if (!emulate_step(regs, instr)) > + goto fail; > > + return true; > + > +fail: > /* > - * emulate_step() could not execute it. We've failed in reliably > - * handling the hw-breakpoint. Unregister it and throw a warning > - * message to let the user know about it. > + * We've failed in reliably handling the hw-breakpoint. Unregister > + * it and throw a warning message to let the user know about it. > */ > - if (!stepped) { > - WARN(1, "Unable to handle hardware breakpoint. Breakpoint at " > - "0x%lx will be disabled.", addr); > - perf_event_disable_inatomic(bp); > - return false; > - } > - return true; > + WARN(1, "Unable to handle hardware breakpoint. Breakpoint at " > + "0x%lx will be disabled.", addr); > + > +disable: > + perf_event_disable_inatomic(bp); > + return false; > } > > int hw_breakpoint_handler(struct die_args *args) > -- > 2.21.0 > >